Operations With Delay Slots - Fujitsu MB91150 Series Hardware Manual

3.7.1

Operations with Delay Slots

During operations with delay slots, a branch occurs at an instruction immediately after
a branch instruction (called a delay slot) before the branch destination instruction is
executed.
I Branch instructions with delay slots
The following branch instructions with delay slots are provided:
JMP:D
BRA:D
BC:D
BV:D
BLE:D
I Explanation of the operation of branch instructions with delay slots
During operation with delay slots, a branch occurs after an instruction immediately after the
branch instruction (called a delay slot) is executed before a branch destination instruction is
executed.
A delay slot instruction is executed before the branch operation. Consequently, the execution
speed appears to be one cycle. If an effective instruction cannot be placed in a delay slot, the
NOP instruction must be placed instead.
[Example]
; Instruction list
ADD R1, R2
BRA:D LABEL
MOV R2, R3
...
LABEL : STR3, @R4 ; Branch destination
In a conditional branch instruction, an instruction placed in a delay slot is executed regardless of
whether a branch condition is met.
For the delayed branch instruction, the execution order of some instructions appears to be
reversed. However, this appearance of reversal applies only for the PC update operation. In
other operations (register update and reference, etc.), the instructions are executed in the
specified order.
A specific example is given below.
@Ri CALL:D label12
label9 BNO:D label9
label9 BNC:D label9
label9 BNV:D label9
label9 BGT:D label9
;
; Branch instruction
; Delay slot: Executed before a branch.
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
CALL:D @Ri RET:D
BEQ:D label9 BNE:D
BN:D label9 BP:D
BLT:D label9 BGE:D
BLS:D label9 BHI:D
label9
label9
label9
label9
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