General Flow Of Data Between The Channels And Processor Storage - IBM 4381 Manual

Processor
Storage
Storage
Control
I
I
A data transfer between processor storage and the channel data buffer handles 64
bytes aligned on a 64-byte boundary, except for beginning and ending transfers for
a processor storage buffer that is not located on a 64-byte boundary. A 64-byte
data transfer requires 1.9 microseconds in a Model Group 1, 2, 3, 11, or 12 ~nd 1.7
microseconds in a Model Group 13 or 14 4381 Processor.
Byte shifter
8
bytes
I
I
Channel Data
Register
8 bytes
Channel Hardware
Channel Data
Buffer Channel in
256 bytes register
L....:=..::.Lt:::::es:..J Channel
out
register
1or2
bytes
Standard
Interface Control 1/0 Interface
Channel 0
Channel 1
Channel 2
Channel
3
Channel
4
Channel 5
Channel6
Channel 7
Channel 8
Channel 9
Channel A
Channel B
Figure 10. General flow of data between the channels and processor storage
Channel control hardware determines the priority for servicing the channels
according to predetermined priorities. When multiple channel trap requests
(requests for microcode service) are outstanding, the lowest numbered channel
with an outstanding request is serviced first. A trap request for this channel will
not be serviced again until the other channels with a request outstanding have one
trap request serviced. That is, each channel is guaranteed not to have to wait for
the servicing of more than an average of five
(if
the optional channels are not
installed) or eleven other trap requests between the servicing of two successive trap
requests of its own (each channel is guaranteed, on an average, every fifth or
eleventh trap service).
The channels are given priority over the instruction processing function for access
to shared facilities. The channels interfere with instruction processing function
operation when a channel trap request is serviced. Trap requests occur for such
operations as data transfer between processor storage and the channel data buffer,
processing of a UCW, command chaining, data chaining, and status handling.
Section 20: 4381 Processor Uniprocessor Model Groups
53