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Chapter 8. Reset and Initialization
This chapter describes reset operations, the initial state of the PPC405GP processor core after a
reset, and an example of the initialization code required to begin executing application code.
Initialization of external system components or system-specific chip facilities must also be performed,
in addition to the basic initialization described in this chapter.
Reset operations affect the PPC405GP at power on time as well as during normal operation, if
programmed to do so. To understand how these operations work it is necessary to first understand
the Signal pins involved as well as the terminology of core, chip and system resets.
8.1
Reset Signals
The PPC405GP provides two reset signals, SysReset and ExtReset. SysReset is bidirectional and
ExtReset is an output.
When the SysReset signal is an input (asserted by an off-chip device), such as during power on reset
(PaR), the chip responds by performing a system reset as described in a following section. An
external assertion of SysReset is not extended by an assertion of the open drain bidirectional
SysReset driver.
As an output, the PPC405GP asserts the SysReset signal when a system reset request is detected.
The SysReset open drain driver is activated and the signal is driven low for 8192 SysClk periods. This
enables the PPC405GP to reset itself and other devices attached to the same reset network.
The Ext Reset signal is used by synchronous peripheral devices served by the PerClk external bus
clock, such as ROM and external bus masters. During chip and system resets, ExtReset is asserted
until the PerClk signal is stable and all internal resets are released.
8.2
Reset Types
Three types of reset, each with different scope, are possible in the PPC405GP. A core reset affects
only the processor core. Chip resets affect the processor core and all on-chip peripherals. System
resets affect the processor core, all on-chip peripherals, and any off-chip devices connected to the
PPC405GP reset net. Refer to chapters describing the on-chip peripherals for detailed information
about their reset behavior.
8.2.1
Core Reset
A core reset results in a reset of the processor core. No other on-chip logic is affected. Clocking logic,
outside the processor core, detects the core reset request and asserts the reset input to the
processor core for a period of 16 processor core clock cycles.
8.2.2
Chip Reset
A chip reset results in the reset of the processor core and on-chip peripherals. Clocking logic detects
the request for a chip reset and asserts the reset input to the processor core for a period of 16
processor core clock cycles. Subsequently, PLL locking is performed as described for a system reset.
Preliminary
Reset and Initialization
8-1
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