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Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
INT3:0
External
Interrupt
Mask
DMA1:0
DMA
Interrupt
Mask
TMR
Timer
Interrupt
Mask
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
8.4.4
Priority Mask Register
The Priority Mask register (Figure 8-9) contains a three-level field that holds a priority value.
This register allows you to mask interrupts based on their priority levels. Write a priority value
to the PM2:0 field to specify the lowest priority interrupt to be serviced. This disables (masks)
any interrupt source whose priority is lower than the PM2:0 value. After reset, the Priority Mask
register is set to the lowest priority (seven), which enables all interrupts of any priority.
Interrupt Mask Register
IMASK
Masks individual interrupt sources
Reset
Bit Name
State
0000 0
0
0
Figure 8-8. Interrupt Mask Register
INTERRUPT CONTROL UNIT
I
I
I
I
N
N
N
N
T
T
T
T
3
2
1
0
Function
Set a bit to mask (disable) interrupt requests
from the corresponding external interrupt pin.
Set to mask (disable) interrupt requests from
the corresponding DMA channel.
Set to mask (disable) interrupt requests from
the timers.
0
D
D
T
M
M
M
A
A
R
1
0
A1202-A0
8-17
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