Iph1; Ipl1; Table 8. Ie1 Special Function Register Definitions; Table 9. Iph1 Special Function Register Definitions - Intel 8XC251SA Hardware Description

Addendum to the 8xc251sa, 8xc251sb, 8xc251sp, 8xc251sq, user’s manual
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3.2.6
IE1
Address: B1H
Reset Value: xxxx xxx0B
Bit Mne-
Bit Number
monic
7 - 1
-
0
ES1
3.2.7

IPH1

Address: B3H
Reset Value: xxxx xxx0B
Bit Mne-
Bit Number
monic
7 - 1
-
0
IPH1.0
3.2.8

IPL1

Address: B2H
Reset Value: xxxx xxx0B
Bit Mne-
Bit Number
monic
7 - 1
-
0
IPL1.0
Interrupt priority of the second serial I/O port can be programmed to one of four levels depending on the
IPH1.0 and IPL1.0 bits.
IPH1.0
IPL1.0
0
0
0
1
1
0
1
1

Table 8. IE1 Special Function Register Definitions

Reserved
Second serial I/O port Interrupt Enable:
Setting this bit enables the second serial I/O port interrupt

Table 9. IPH1 Special Function Register Definitions

Reserved
Second serial I/O port Interrupt Priority High Bit

Table 10. IPL1 Special Function Register Definitions

Reserved
Second serial I/O port Interrupt Priority Low Bit

Table 11. Interrupt Priority of Second Serial I/O Port

0 (Lowest Priority)
1
2
3 (Highest Priority)
8xC251Tx Hardware Description
Function
Function
Function
Priority Level
11

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