Serial Eeprom For 82562Ez(Ex) Implementations; Lan Disable Circuitry; 82562Ez(Ex) Memory Layout (128 Byte Eeprom) - Intel 82562EZ Design Manual

Super IO
GP Port
or
ICHx GPIO
24, 25, 27, 28
or
µController
(mobile)
Figure 5. LAN Disable Circuitry
Note: The 100 Ω resistors for the Test Mode signals are required for the Exclusive OR (XOR) Tree and
Isolate Mode.
3.2.2

Serial EEPROM for 82562EZ(EX) Implementations

Serial EEPROM for LAN implementations based on 82562EZ(EX) devices connects to the ICH5.
Depending upon the size of the EEPROM, the 82562EZ(EX) may or may not support legacy
manageability.
details on the EEPROM, refer to the appropriate I/O Control Hub 2, 3, 4, 5, 6, and 7 EEPROM
Map and Programming Information.
Table 7.
NOTE: No manageability provided.
3.3Vstb
1K
3.3Vstb
RST#
Sensor/
Supervisor
Table 7 and Table 8 list the EEPROM map for the 82562EZ(EX) PLC device. For

82562EZ(EX) Memory Layout (128 Byte EEPROM)

00h
HW/SW Reserved Area
3Fh
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
3.3Vstb
470 Ω
MMBT3904
1K
LAN_RST#
ICHx
RSMRST#
100 Ω
TESTEN
100 Ω
ISOL_TCK
100 Ω
ISOL_TI
100 Ω
ISOL_TEX
13