Source Synchronous Signals General Routing Guidelines; Figure 6. Common Clock Topology; Table 3. Processor And Gmch Psb Common Clock Signal Package Lengths And Minimum Board Trace Lengths - Intel 855GM Design Manual

Intel Pentium M/Celeron M Front Side Bus Design Guidelines
BR0# = X mils board trace + 336 CPU PKG + 465 GMCH PKG = 2212 pad-to-pad length
Therefore: X = BR0# board trace = 2212 - 336 - 465 = 1411 pin to pin length.

Figure 6. Common Clock Topology

Table 3. Processor and GMCH PSB Common Clock Signal Package Lengths and Minimum Board
Trace Lengths
Signal Names
CPU
ADS#
BNR#
BPRI#
BR0#
DBSY#
DEFER#
DPWR#
DRDY#
HIT#
HITM#
LOCK#
RS0#
RS1#
RS2#
TRDY#
RESET#
4.1.3.

Source Synchronous Signals General Routing Guidelines

All source synchronous signals use an AGTL+ bus driver technology with on-die GTL termination
resistors connected in a point-to-point, Zo = 55 Ω controlled impedance topology between the processor
and the GMCH. No external termination is needed on these signals. Source synchronous PSB address
signals operate at a double pumped rate of 200 MHz while the source synchronous PSB data signals
operate at a quad pumped rate of 400 MHz. High-speed operation of the source synchronous signals
40
Processor
Pad
Package Length
Intel Pentium
GMCH M/Celeron
Processor
ADS# 454
BNR# 506
BPRI# 424
BR0# 336
DBSY# 445
DEFER# 349
DPWR# 506
DRDY# 529
HIT# 420
HITM# 368
HLOCK# 499
RS0# 576
RS1# 524
RS2# 451
HTRDY# 389
CPURST# 455
Length L1
Package trace
Motherboard PCB trace
Total Pad-to-Pad Min.
Length Requirements
L1 (mils)
GMCH
761 2212
408 2212
573 2212
465 2212
608 2212
572 2212
518 2212
347 2212
489 2212
641 2212
515 2212
321 2212
495 2212
514 2212
511 2212
656 2212
®
Intel 855GM/855GME Chipset Platform Design Guide
GMCH
Pad
Min. Board Trace Length
(mils)
997
1298
1215
1411
1159
1291
1188
1336
1303
1203
1198
1315
1193
1247
1312
1101
R