Source Synchronous (Ss) Signals; Figure 7. Processor Topology; Table 2. Processor System Bus Data Signal Routing Guidelines; Table 3. Processor System Bus Address Signal Routing Guidelines - Intel 852GME Design Manual

R
thickness, line width, and velocity of the signals will be uniform across a single layer of the stackup.
There is no guarantee of a relationship of dielectric thickness, line width, and velocity between layers.

Figure 7. Processor Topology

4.3.5.

Source Synchronous (SS) Signals

Table 2. Processor System Bus Data Signal Routing Guidelines

Signal Names
CPU
DBI[3:0]#
D[63:0]#
DSTBN[3:0]#
DSTBP[3:0]#
The Data signals within each group must be routed to within ± 0.100 inches of its associated "reference"
NOTE:
strobe. The complement strobe must be routed to within ± 0.025 inches of the associate "reference" strobe.
All traces within each signal group must be routed on the same layer (required). Intel recommends that
length of the strobes be centered to the average length of associated data or address traces to maximize
setup/hold time margins.

Table 3. Processor System Bus Address Signal Routing Guidelines

Signal Names
CPU
A[31:3]#
REQ[4:0]#
ADSTB[1:0]#
The Address signals within each group must be routed to within ± 0.200 of its associated strobe. All traces
NOTE:
within each signal group must be routed on the same layer (required). It is recommended that length of the
strobes be centered to the average length of associated data or address traces to maximize setup/hold time
margins. Please refer to Mobile Intel
supporting Hyper-Threading Technology on 90-nm process technology Datasheet for signals and
associated strobe.
® ®
Intel 852GME, Intel 852GMV and Intel
Processor
Pad
Package trace
Motherboard PCB trace
Transmission
Line Type
GMCH
DINV[3:0]# Strip-line
HD[63:0]# Strip-line
HDSTBN[3:0]# Strip-line
HDSTBP[3:0]# Strip-line
Transmission
Line Type
GMCH
HA[31:3]# Strip-line
HREQ[4:0]# Strip-line
HADSTB[1:0]# Strip-line
®
Pentium
®
852PM Chipset Platforms Design Guide
Length L1
GMCH
Total Trace Length
Nominal
Impedance
Min Max
(inches) (inches)
1.0 6.0 53 ± 15%
1.0 6.0 53 ±15%
1.0 6.0 53 ± 15%
1.0 6.0 53 ±15%
Total Trace Length
Nominal
Impedance
( )
Min Max
(inches) (inches)
1.0 6.0 53 ± 15%
1.0 6.0 53 ± 15%
1.0 6.0 53 ± 15%
®
4 Processor Datasheet orMobile Intel
FSB Design Guidelines
Pad
Width & Spacing (mils)
( )
4.5 & 11.5
4.5 & 11.5
4.5 & 11.5
4.5 & 11.5
Width & Spacing (mils)
4.5 & 9
4.5 & 9
4.5 & 9
® ®
Pentium 4 Processor
45