31.15.61 Otg_Fs/Otg_Hs Register Map; Table 231. Otg_Fs/Otg_Hs Register Map And Reset Values - ST STM32F446 Series Reference Manual

RM0390
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 GATEHCLK: Gate HCLK
Bit 0 STPPCLK: Stop PHY clock

31.15.61 OTG_FS/OTG_HS register map

The table below gives the USB OTG register map and reset values.

Table 231. OTG_FS/OTG_HS register map and reset values

Register
Offset
name
OTG_
GOTGCTL
0x000
Reset value
OTG_
GOTGINT
0x004
Reset value
OTG_
GAHBCFG
0x008
Reset value
OTG_
GAHBCFG
0x008
Reset value
OTG_
GUSBCFG
0x00C
Reset value
OTG_
GUSBCFG
0x00C
Reset value
OTG_
GRSTCTL
0x010
Reset value 1
The application sets this bit to gate HCLK to modules other than the AHB Slave and Master
and wakeup logic when the USB is suspended or the session is not valid. The application
clears this bit when the USB is resumed or a new session starts.
The application sets this bit to stop the PHY clock when the USB is suspended, the session
is not valid, or the device is disconnected. The application clears this bit when the USB is
resumed or a new session starts.
0 0
0 0 0 0 0
USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
0 0 0 0 0 1
0 0 0 0
0 0 0 0 0 0 0
RM0390 Rev 4
0 0 0 0 0 0 0 0
0 0
0 0
0 0 0
TRDT
0 1 0 1 0 0 1
TRDT
0 1 0 1 0 0 1
TXFNUM
0 0 0 0 0 0
0 0 0 0 0
0
0
HBSTLEN
0 0 0 0 0
TOCAL
0 0 0
TOCAL
0 0 0
0 0 0 0
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