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Getting Started With TPS65910 and OMAPL-137, OMAPL-138, and TMS320C6742/6/8 Processors
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4.1.3
Backup Battery Configuration
If the system has a backup battery, set the BBCHEN bit to 1 in the BBCH_REG register, to enable backup
battery charging. The maximum voltage to which the backup battery is charged is set by the BBSEL bits.
4.1.4
DCDC and Voltage Scaling Resource Configuration
Set DEVCTRL_REG[SR_CTL_I2C_REG] = 1 to control register using the control I
SCLSR_EN1 and SDASR_EN2 signals, the user can control the power resources. For OMAPL series, the
following example is provided:
•
SMPS control:
– Configure two operating voltages for DCDC1 and DCDC2:
•
VDDx_OP_REG.SEL= Roof voltage (ENx ball high)
•
VDDx_SR_REG.SEL = Floor voltage (ENx ball low)
– Assign control for VDD1 to SCLSR_EN1:
•
Set EN1_SMPS_ASS_REG.VDD1_EN1 = 1
•
Set SLEEP_KEEP_RES_ON_REG.VDD1_KEEPON = 1 (allow low-power mode)
•
LDO control:
– Assign control for VMMC regulator (for example, can be used for any other set of registers).
– Set EN2_LDO_ASS_REG.VMMC_EN2 = 1
– When SDASR_EN2 control signal is high then the regulator output depends on
SLEEP_KEEP_LDO_ON setting.
– SDASR_EN2 = 1, VMMC status is active.
– SDASR_EN2 = 0 then:
•
SLEEP_KEEP_LDO_ON[VMMC_KEEPON] = 0, VMMC output is off.
•
SLEEP_KEEP_LDO_ON[VMMC_KEEPON] = 1, VMMC output is on in LOW-POWER state.
4.1.5
Sleep Platform Configuration
Configure the state of the LDOs when the SLEEP signal is used (by default all resources go into SLEEP
state; in SLEEP state the LDO voltage is maintained but transient and load capability are reduced).
Resources that must provide full load capability must be set in the SLEEP_KEEP_LDO_ON_REG register.
Resources that can be set off in SLEEP state to optimize power consumption must be set in the
SLEEP_SET_LDO_OFF_REG register.
4.2
Event Management Through Interrupts
4.2.1
INT_STS_REG.VMBHI_IT
INT_STS_REG.VMBHI_IT indicates that the supply (VBAT) is connected (leaving the BACKUP or NO
SUPPLY state), the system must be initialized. (See
4.2.2
INT_STS_REG.PWRON_IT
INT_STS_REG.PWRON_IT is triggered when the PWRON button is pressed. If device is in OFF or
SLEEP state, then this acts as a wake-up event and resources are reinitialized.
4.2.3
INT_STS_REG.PWRON_LP_IT
INT_STS_REG.PWRON_LP_IT is the PWRON long-press interrupt. This interrupt is generated when the
PWRON button is pressed for 6 seconds. The application processor can make a decision to acknowledge
the interrupt. If this interrupt is not acknowledged in the next 2 seconds then the device interprets this as a
power-down event.
SWCU071B – December 2010 – Revised October 2015
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Section
TPS65910 User Guide For OMAPL-137, OMAPL-138, and TMS320C674x
Copyright © 2010–2015, Texas Instruments Incorporated
2
C interface. Using the
4.1, First Initialization.)
Family of Processors
11
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