Fujitsu F2MC-16LX Hardware Manual page 254

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
I Control status register (ICS01)
The control status register (ICS01) has the bit configuration shown below.
Figure 12.2-16 Bit configuration of control status register (ICS01)
000060
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Control status register
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000
The control status register (ICS01) consists of bits that have the functions explained below.
[Bits 7, 6] ICP1, ICP0
These bits are the interrupt flags of input capture. When a valid edge of the external input pin
is detected, this bit is set to "1". If the interrupt permit bit (ICE1, ICE0) is set, an interrupt may
occur when a valid edge is detected.
This bit is cleared when "0" is written. Writing "1" has no effect. An instruction of the read-
modify-write type always reads "1".
0
1
• ICP1: Corresponds to input capture 1
• ICP0: Corresponds to input capture 0
[Bits 5, 4] ICE1, ICE0
These bits are used as the interrupt permit bits of input capture. If this bit is set to "1" and the
interrupt flag (ICP1, ICP0) is set, then an input capture interrupt occurs.
0
1
• ICE1: Corresponds to input capture 1
• ICE0: Corresponds to input capture 0
[Bits 3, 2, 1, 0] EG11, EG10, EG01, EG00
These bits specify the valid edge polarity of external input. Also, they are used to specify the
enable of input capture operations.
EG11/EG01
0
0
1
1
• EG11/EG10: Corresponds to input capture 1
• EG01/EG00: Corresponds to input capture 0
238
7 6 5 4
No valid edge detected (initial value)
Valid edge detected
Interrupt prohibit (initial value)
Interrupt permit
EG10/EG00
0
1
0
1
3 2 1 0
Edge detect polarity
No edge detected (stop state) (initial value)
Rising edge detected
Falling edge detected
Both edges detected
ICS01
B