Fujitsu F2MC-16LX Hardware Manual page 366

CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT
I Interrupt/DTP source register (EIRR: External interrupt request register)
The bit configuration of the interrupt/DTP source register (EIRR) is shown below.
EIRR
Address: 00000D
H
The interrupt/DTP source register (EIRR) is used in read operations to indicate whether a
corresponding external interrupt/DTP request exists. In write operations, the register is used to
clear the flip-flop for the request. If a register bit returns "1" in a read operation, the pin
corresponding to this bit carries an external interrupt/DTP request. By setting "0", the request
flip-flop corresponding to the bit is cleared. Writing "1" has no effect. Read-modify-write
instructions always return "1".
Note:
Reading by read-modify-write type instructions always returns "1". If multiple external
interrupt request outputs are enabled (ENIR: EN7 to EN0=1), only the bits for which the CPU
accepts an interrupt (bits for which "1" was set in ER3 to ER0) are cleared. No other bits
must be cleared unconditionally.
I Request level setting register (ELVR: External level register)
The bit configuration of the request level setting register (ELVR) is shown below.
Address: 00000E
Address: 00000F
The request level setting register (ELVR) is used to select a request detection level. Two bits
are assigned for each pin, as shown in Table Table 18.2-1 "ELVR assignment (LA0 to LA7, LB0
to LB7)". If the setting for a request input indicates a level, the corresponding level will be set
again when it is cleared, provided the input is active.
Table 18.2-1 ELVR assignment (LA0 to LA7, LB0 to LB7)
LBx
0
0
1
1
350
15 14 13 12
ER7 ER6 ER5 ER4 ER3
R/W R/W R/W R/W R/W
7 6 5
LB3 LA3 LB2
H
R/W R/W R/W R/W R/W
15 14 13
LB7 LA7 LB6
H
R/W R/W R/W R/W R/W
LAx
0 Request by "L" level
1 Request by "H" level
0 Request by rising edge
1 Request by falling edge
11 10 9 8
ER2 ER1 ER0
R/W R/W R/W
4 3 2 1
LA2 LB1 LA1 LB0
R/W R/W R/W
12 11 10 9
LA6 LB5 LA5 LB4
R/W R/W R/W
Operation
Initial value
00000000
B
--- (However, the applicable
value is different for read
and write operations)
0 Initial value
LA0 00000000
B
8 Initial value
LA4 00000000
B