Fujitsu F2MC-16LX Hardware Manual page 548

APPENDIX
Table B.5-2 Cycle count correction values for counting execution cycles
Internal register
Internal memory
Even address
Internal memory
Odd address
External data bus
16-bit even address
External data bus
16-bit odd address
External data bus
8-bits
*1: (b), (c), and (d) are used for
Instruction List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to
wait by ready input or automatic ready must also be added.
Table B.5-3 Cycle count correction values for counting instruction fetch cycles
Internal memory
External data bus 16-bits
External data bus 8-bits
Note:
• When an external data bus is used, the cycle counts during which an instruction is made to
wait by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
532
Operand
Cycle
count
+0
+0
+0
+1
+1
+1
Instruction
(*1)
(b) byte (c) word
Access Cycle
count count
1 +0
1 +0
1 +2
1 +1
1 +4
1 +4
(cycle count) and B (correction value) in B.8 "F
Byte boundary
-
-
+3
(*1) (*1)
(d) long
Access Cycle Access
count count count
1 +0
1 +0
2 +4
1 +2
2 +8
2 +8
2
MC-16LX
Word
boundary
+2
+3
-
2
2
4
2
4
4