Fujitsu F2MC-16LX Hardware Manual page 271

[Bit 12] CLKS (built-in prescaler select)
This bit is used to select the frequency of a built-in prescaler in the selection of the timer
mode.
It is valid in the timer mode, and only decrementing (down count) is permitted.
CLKS
0 2 machine cycles (initial value)
1 8 machine cycles
If this bit is rewritten after its start, the count value is not assured.
[Bits 11 to 10] CMS1, CMS0 (count mode selection)
These bits are used to select the count mode.
CMS1 CMS0
0 0
0 1
1 0
1 1
If this bit is rewritten after its start, the count value is not assured.
[Bits 9 to 8] CES1, CES0 (count clock edge selection)
These bits are used to select the detect edge of external pins AIN and BIN in the up/down
count mode.
This setting is invalid in modes other than up/down count.
CES1 CES0
0 0
0 1
1 0
1 1
If this bit is rewritten after its start, the count value is not assured.
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
Internal clock selected
Count mode
Timer mode [decremented] (initial value)
Up/down count mode
Phase difference count mode: frequency multiplied by 2
Phase difference count mode: frequency multiplied by 4
Selected edge
Edge detect prohibit (initial value)
Falling edge detect
Rising edge detect
Both rising and falling edges detected
255