Fujitsu F2MC-16LX Hardware Manual page 348

CHAPTER 17 8/16-BIT PPG TIMER
Figure 17.1-2 Block diagram of the 8/16-bit PPG timer (channels 1/3/5)
Peripheral clock: divide-by-16
Peripheral clock: divide-by-8
Peripheral clock: divide-by-4
Peripheral clock: divide-by-2
Peripheral clock
Count clock
select
Timebase counter output
Main clock: divide-by-512
L/H select
332
PPG1/3/5 output enable
PPG1/3/5 output latch
PCNT (down-counter)
L/H selector
PRLL PRLBH
PRLL
PPG1/3/5
A/D converter
PEN1
S
R Q
PUF0 PIE0
PPGC1
(operation mode control)
L data bus
H data bus
IRQ