Fujitsu F2MC-16LX Hardware Manual page 204

CHAPTER 8 I/O PORT
I Analog input enable register (ADER)
The bit configuration of the analog input enable register (ADER) is shown in the figure below.
ADER
Address:00001F
The analog input enable register (ADER) controls the pins of port 6 as follows:
• 0: Sets the port I/O mode
• 1: Set the analog I/O mode. "1" is restored by a reset.
I Up/down timer input enable register (UDER)
The bit configuration of the up/down timer input enable register (UDER) is shown in the figure
below.
UDER
Address:00000B
The up/down timer input enable register (UDER) controls the pins of port 6 as follows:
• 0: Sets the port I/O mode
• 1: Sets the up/down timer input mode. "1" is restored by a reset.
In the MB90470 series, each bit is set as follows:
• UDE0: P30/AIN0
• UDE1: P31/BIN0
• UDE2: P32/ZIN0
• UDE3: P33/AIN1
• UDE4: P34/BIN1
• UDE5: P35/ZIN1
188
7 6 5
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
H
7 6 5
- - UDE5 UDE4 UDE3 UDE2 UDE1 UDE0
H
4 3 2 1
4 3 2 1
0 Initial value Access
11111111 R/W
0 Initial value Access
XX000000 R/W