Chip Selection Area Register (Carx) - Fujitsu F2MC-16LX Hardware Manual

23.2.2 Chip Selection Area Register (CARx)

This section describes the configuration and functions of the chip selection area
register (CARx).
I Chip selection area register (CARx)
The diagram below shows the bit configuration of the chip selection area register (CARx).
0000C1
H
0000C3
H
0000C5 (R/W) (R/W) (R/W) (R/W) (R/W)
H
0000C7
H
[bit7-0]A7-A0
[Bit 7-0] A7-A0
These bits are used to set the address decode area for the chip select pin. They specify the
upper 8 bits of the address value, allowing an address within 64 KB to be specified.
Note:
The chip selection facility is not active for internal accesses such as access to built-in RAM,
built-in ROM, and built-in I/O area.
15 14 13 12
A7 A6 A5 A4
(1) (1) (1) (1)
CHAPTER 23 CHIP SELECTION FACILITY
11 10 9 8
A3 A2 A1 A0
(W) (R/W) (R/W)
(1) (1) (1) (1)
CARx
Chip select control register
Read/write
Initial value
443