Fujitsu F2MC-16LX Hardware Manual page 244

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
I Block diagram of 16-bit free-running timer
Figure 12.2-5 "Block diagram of 16-bit free-running timer" is a block diagram of the 16-bit free-
running timer.
Compare
I Compare clear register (CPCLR)
Figure 12.2-6 "Bit configuration of the compare clear register (CPCLR)" shows the bit
configuration of the compare clear register (CPCLR).
Figure 12.2-6 Bit configuration of the compare clear register (CPCLR)
15
000067 CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXX
000066 CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXX
The compare clear register is a 16-bit compare register used to make a comparison with the 16-
bit free-run timer. An initial value of a register value is undefined. Therefore, set the initial value,
then allow the activation. This register requires word access. When this register value matches
the value of the 16-bit free-run timer, the 16-bit free-run timer value is initialized to 0000
compare clear interrupt flag is set. When interrupt operation is allowed, an interrupt request is
issued to the CPU.
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Figure 12.2-5 Block diagram of 16-bit free-running timer
IVF IVF STOP MODE
16-bit free-running timer
16-bit compare clear register
MSI2 to 0
circuit
14 13 12
7 6 5 4
Interrupt request
SCLR CLK2 CLK1 CLK0
Counter value output T15 to T00
ICLR ICRE
11 10 9 8
3 2 1 0
φ
Divider
Clock
Interrupt request
CPCLR
Compare clear register
CPCLR
Compare clear register
B
B
and a
H