Operations Of The 16-Bit Reload Timer - Fujitsu F2MC-16LX Hardware Manual

16.3 Operations of the 16-Bit Reload Timer

This section describes the settings of the 16-bit reload timer and the state transitions
during counter operation.
I Settings of the 16-bit reload timer
❍ Settings for internal clock mode
For interval timer operation, the settings shown in Figure 16.3-1 "Settings of internal clock
mode" are required.
15 14
TMCSR -
TMRLR
: Bit used
1 : Set to 1
❍ Settings for event counter mode
For event counter mode operation, the settings shown in Figure 16.3-2 "Settings of event
counter mode" are required.
15 14
TMCSR -
TMRLR
DDR9
: Bit used
1 : Set to 1
: Set the bit corresponding to the used pin to "0."
Figure 16.3-1 Settings of internal clock mode
13 12 11 10
- - - CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
Other than "11"
Initial counter value setting (reload value)
Figure 16.3-2 Settings of event counter mode
13 12 11 10
- - - CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
Other than "11"
Initial counter value setting (reload value)
CHAPTER 16 16-BIT RELOAD TIMER
9 8 7 6 5
9 8 7 6 5
4 3 2 1 0
UF CNTE TRG
1
4 3 2 1 0
UF CNTE TRG
1
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