Fujitsu F2MC-16LX Hardware Manual page 405

Figure 20.3-1 State transitions during operation of expanded I/O serial interface
Transfer end
STRT=0, BUSY=0
MODE=0
MODE=0
STOP=0
&
&
STOP=0
STRT=1 &
End
Transfer operation
STRT=1, BUSY=1
Figure 20.3-2 Concept of read and write of serial data registers
Data bus
SOT
Read
SIN
Write
Interrupt output
Expanded I/O
serial interface
1. For MODE = 1, data transfer is ended by the shift clock counter. A read/write Wait state will
be entered after SIR is set to 1. If the SIE bit is "1", an interrupt signal is generated. An
interrupt signal will not be generated; however, if the SIE is inactive or when data transfer is
stopped by setting the STOP bit by writing "1".
2. As soon as the serial data register is read or written, the interrupt request will be cleared and
serial transfer will start.
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE
STOP=0 & STRT=0
STOP=1
STOP=1
STRT=1
MODE = 1 / End / STOP = 0
SDR R/W & MODE=1
Data bus
Read
Write
(1)
Interrupt input
(2)
Data bus
Reset
STOP
STRT=0, BUSY=0
STOP=0
&
STOP=1
Serial data register R/W Wait
STRT=1, BUSY=0
MODE=1
CPU
Interrupt controller
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