8/16-Bit Up/Down Counter/Timer Operation - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER

13.3 8/16-bit Up/Down Counter/Timer Operation

This section explains different count modes in the 8/16-bit up/down counter/timer and
the operation of the reload/compare function.
I Selection of count mode
The 8/16-bit up/down counter/timer has 4 types of count modes. These count modes are
selected with CCRH: CMS1 or 0.
Table 13.3-1 Selection of count mode
CMS1, CMS0
00B
01B
10B
11B
❍ Timer mode (decremented)
In the timer mode, output of the internal prescaler is decremented. The built-in prescaler
enables selection of either 2 machine cycles or 8 machine cycles with CCRH: CLKS.
❍ Up/down count mode
In the up/down count mode, counting the input of external pins AIN and BIN enables an up/
down count. AIN pin input controls increments, and BIN pin input controls decrements.
Input of the AIN pin and BIN pin indicates an edge detect, enabling selection of a detect edge
with CCRH: CES1 and CES0.
Table 13.3-2 Selection of count mode
CES1, CES0
00B
01B
10B
11B
❍ Phase difference count mode (at frequency multiplied by 2/frequency multiplied by 4)
In the phase difference count mode, to count the encoder phase difference between output
signal phases A and B, the BIN pin input level is checked for counting if the AIN pin input edge
is detected, and the AIN pin input level is checked for counting if the BIN pin input edge is
detected.
In the modes at frequency multiplied by 2 and frequency multiplied by 4, the phase difference is
checked between AIN and BIN pin inputs. If the AIN pin is advanced, it is incremented and, if
the BIN pin is advanced, it is decremented.
264
Count mode
Timer mode (decremented)
Up/down count mode
Phase difference count mode: frequency multiplied by 2
Phase difference count mode: frequency multiplied by 4
Detect edge
Edge detect prohibit
Falling edge detect
Rising edge detect
Both falling and rising edges detected