Fujitsu F2MC-16LX Hardware Manual page 98

CHAPTER 3 INTERRUPT
❍ Extended Intelligent I/O service (EI
2
The EI OS descriptor is located from "000100
containing 8 bytes x 16 channels to set the transfer mode, peripheral resource address, the
number of bytes to transfer, and the transfer destination address. Channels are set by the
interrupt control register (ICR).
Note:
CPU programs are not executed during the execution of the Extended Intelligent I/O service
2
(EI OS).
I Operation of the Extended Intelligent I/O Service (EI
Figure 3.7-1 Extended Intelligent I/O Service (EI
2
ISD : EI OS
I/OA : I/O address pointer
BAP : Buffer address pointer
2
ICS : EI OS channel setting bit in the interrupt control register (ICR)
DCT: Data counter
1. A peripheral resource outputs an interrupt request.
2. The interrupt controller sets the EI
control registers (ICRs).
3. The transfer source and destination are read from the EI
4. Data is transferred between the peripherals resource and memory.
5. Upon completion of data transfer, the interrupt request flag bit of the peripheral resource is
cleared to "0".
82
Memory space
by I/OA
Resource
register
CPU
(3)
ISD
(3)
by BAP
(4)
Buffer
OS descriptor
2
OS) descriptor (ISD)
" to "00017F
H
2
OS)
2
OS) Operation
Peripheral function (resource)
Resource register
Interrupt request
by ICS
(2)
Interrupt control register (ICR)
Interrupt controller
by DCT
2
OS descriptor according to the settings in the interrupt
2
OS descriptor.
" in RAM, serving as a register
H
(5)
(1)