Fujitsu F2MC-16LX Hardware Manual page 251

• OTD1: Corresponds to output compare 1/3/5
• OTD0: Corresponds to output compare 0/2/4
[Bits 7, 6] ICP1, ICP0
These bits are the interrupt flags for output compare. Set them to "1" if the compare register
and 16-bit free-running timer have matching values. If the interrupt request bit (ICE1, ICE0)
is set to "enabled", an output compare interrupt occurs. This bit is cleared if "0" is written.
Writing "1" has no effect. An instruction of the read-modify type only reads "1".
0 No compare match (initial value)
1 Compare match
• ICP1: Corresponds to output compare 1/3/5
• ICP0: Corresponds to output compare 0/2/4
[Bits 5, 4] ICE1, ICE0
These bits are the interrupt permit bits of output compare. If these bits are set to "1" and an
interrupt flag (ICP1, ICP0) is set, an output compare interrupt occurs.
0 Output compare interrupt prohibit (initial value)
1 Output compare interrupt permit
• ICE1: Corresponds to output compare 1/3/5
• ICE0: Corresponds to output compare 0/2/4
[Bits 3, 2] Unused bits
These bits are not used.
[Bits 1, 0] CST1, CST0
These bits permit a matching operation with the 16-bit free-running timer.
0 Compare operation prohibit (initial value)
1 Compare operation permit
• CST1: Corresponds to output compare 1/3/5
• CST0: Corresponds to output compare 0/2/4
Before a compare operation is permitted, specify the compare register value.
Note:
Output compare operates in sync with the 16-bit free-running timer clock. Thus, if the 16-bit
free-running timer stops, the compare operation also stops.
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
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