Fujitsu F2MC-16LX Hardware Manual page 161

from an instruction next to the instruction that was processed before the stop mode was set.
Note:
• When executing an interrupt, an instruction next to the instruction that specified the Stop
mode is normally executed first before an interrupt request is processed. If a change to the
stop mode occurs at the same time as an external bus hold request is received, an interrupt
may be executed first before the next instruction is executed.
• In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from
PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait time and
PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for the
main clock and PLL clock are counted simultaneously according to the value specified in the
oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection
register. The oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the
clock selection register must be selected accordingly to account for the longer of main clock
and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization wait
time, however, requires 2
selection bits (CKSCR: WS1, WS0) in the clock selection register to "10
Figure 6.5-3 "Cancel operation of stop mode (external reset)" shows the cancel operation of the
stop mode.
Figure 6.5-3 Cancel operation of stop mode (external reset)
RST pin
Stop mode
Main clock
PLL clock
CPU clock
CPU operation
CHAPTER 6 LOW-POWER CONSUMPTION MODE
14
/HCLK or more. Set the oscillation stabilization wait time
Oscillation stabilization wait
Not operating
Not operating
Reset cancel
Stop-mode cancel
" or "11
B
During oscillation
Main clock
Processing
Sequence for resetting
".
B
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