Fujitsu F2MC-16LX Hardware Manual page 13

17.2 8/16-bit PPG Timer Registers ............................................................................................................ 333
17.2.1 PPG0/2/4 Operation Mode Control Register (PPGC0) ................................................................. 334
17.2.2 PPG1/3/5 Operation Mode Control Register (PPGC1) ................................................................. 336
17.2.3 PPG0 to PPG5 Output Control Registers (PPG0/1, PPG2/3, PPG4/5) ........................................ 339
17.2.4 Reload Registers (PPLL0 to PPLL5, PPLH0 to PPLH5) .............................................................. 341
17.3 Operations of 8/16-Bit PPG Timer ..................................................................................................... 342
CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT ........................................................ 347
18.1 Overview of DTP/External Interrupt Unit ............................................................................................ 348
18.2 DTP/External Interrupt Unit Registers ............................................................................................... 349
18.3 Operations of DTP/External Interrupt Unit ......................................................................................... 351
18.4 Notes on DTP/External Interrupt Unit Usage ..................................................................................... 353
CHAPTER 19 8/10-BIT A/D CONVERTER ...................................................................... 355
19.1 Overview of 8/10-bit A/D Converter ................................................................................................... 356
19.2 8/10-bit A/D Converter Registers ....................................................................................................... 358
19.2.1 Control Status Register 1 (ADCS1) .............................................................................................. 359
19.2.2 Control Status Register 2 (ADCS2) .............................................................................................. 362
19.2.3 Data Registers (ADCR2 and ADCR1) .......................................................................................... 365
19.3 Operations of 8/10-bit A/D Converter ................................................................................................ 366
19.3.1 Example of µDMA Start in Single Mode ....................................................................................... 368
19.3.2 Example of µDMA Start in Continuous Mode ............................................................................... 370
19.3.3 Example of µDMA Start in Stop Mode .......................................................................................... 372
19.4 Conversion Data Protection Function ................................................................................................ 374
19.5 Precautions When Using the 8/10-bit A/D Converter ........................................................................ 376
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE ..................................................... 377
20.1 Overview of Expanded I/O Serial Interface ........................................................................................ 378
20.2 Registers of Expanded I/O Serial Interface ....................................................................................... 379
20.2.1 Serial Mode Control Status Register (SMCS) .............................................................................. 380
20.2.2 Serial Shift Data Register (SDR) .................................................................................................. 384
20.2.3 Dedicated Prescaler Control Register (SDCR) ............................................................................. 385
20.3 Operation of Expanded I/O Serial Interface ....................................................................................... 386
20.3.1 Shift Clock Modes ......................................................................................................................... 387
20.3.2 Operational States of Serial I/O Units ........................................................................................... 388
20.3.3 Start/Stop Timing and Input/Output Timing of Shift Operation ..................................................... 390
20.3.4 Interrupt Function ......................................................................................................................... 392
CHAPTER 21 UART ......................................................................................................... 393
21.1 Overview of the UART ....................................................................................................................... 394
21.2 UART Registers ................................................................................................................................. 396
21.2.1 Serial Mode Register (SMR) ......................................................................................................... 397
21.2.2 Serial Control Register (SCR) ...................................................................................................... 399
21.2.3 Serial Input/Output Register (SIDR/SODR) .................................................................................. 401
21.2.4 Serial Status Register (SSR) ........................................................................................................ 402
21.2.5 Communication Prescaler Control Register (CDCR) .................................................................... 404
21.3 UART Operations .............................................................................................................................. 406
21.3.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .................................................... 410
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