Fujitsu F2MC-16LX Hardware Manual page 70

CHAPTER 3 INTERRUPT
Table 3.3-3 Interrupt control registers (ICR00 to ICR15) bit configuration
ICS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
54
ICS2 ICS1 ICS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2
EI OS channel setting bits
Channel Descriptor address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
100h
108h
110h
118h
120h
128h
130h
138h
140h
148h
150h
158h
160h
168h
170h
178h