Fujitsu F2MC-16LX Hardware Manual page 90

CHAPTER 3 INTERRUPT
Table 3.6-1 Relationship between channel number and descriptor address (Continued)
DMA enable
register
EN10
EN11
EN12
EN13
EN14
EN15
74
Descriptor
Channel
address
10 000150
H
11 000158
H
12 000160
H
13 000168
H
14 000170
H
15 000178
H
Resource interrupt request
Output compare (channel 2) match
UART transmit completed
16-bit FRT/16-bit reload timer overflow
SI01
SI02
A/D