Fujitsu F2MC-16LX Hardware Manual page 249

I Block diagram of output compare
Figure 12.2-10 "Block diagram of output compare" is a block diagram of output compare.
16-bit timer counter value (T15 to T00)
16-bit timer counter value (T15 to T00)
I Compare register (OCCP0 to 5)
Compare register (OCCP0 to 5) has the bit configuration shown below.
Figure 12.2-11 Bit configuration of compare register (OCCP0 to 5)
00004B
H
00004D
15
H
00004F
H
C15
000051
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXX
000053
H
000055
H
00004A
H
00004C
H
00004E
H
C07
000050
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXX
000052
H
000054
H
The compare register (OCCP0 to 5) is a 16-bit register used to comparison with the 16-bit free-
running timer. The register has unspecified initial values, thus the start of operation must be
enabled after the values are specified. This register uses word access. If this register and the
16-bit free-running timer have matching values, a compare signal is generated to set the output
compare interrupt flag. If output enable is given, the output level corresponding to the compare
register is reversed.
Figure 12.2-10 Block diagram of output compare
Compare control
Compare register 0 (2) (4)
Compare control
Compare register 1 (3) (5)
ICP1
Control section
Control blocks
14 13 12
C14 C13 C12
7 6 5 4
C06 C05 C04
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
T Q OTE0
CMOD
T Q OTE1
ICP0 ICE0 ICE0
Compare 1 (3) (5) interrupt
Compare 0 (2) (4) interrupt
11 10 9 8
C11 C10 C09 C08
3 2 1 0
C03 C02 C01 C00
OUT0 (2) (4)
OUT1 (3) (5)
OCCP0 to 5
Compare register
OCCP0 to 5
Compare register
B
B
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