Fujitsu F2MC-16LX Hardware Manual page 69

I Function of each bit in interrupt control register (ICR00 to ICR15)
❍ Interrupt level setting bits (IL2 to IL0)
This specifies the corresponding interrupt level in the peripheral function. A reset initializes the
bit to level 7 (no interrupts). Table 3.3-2 "Relationship between interrupt level setting bits and
interrupt levels" lists the relationship between interrupt level setting bits and every interrupt level.
Table 3.3-2 Relationship between interrupt level setting bits and interrupt levels
IL2
0
0
0
0
1
1
1
1
❍ Extended intelligent I/O (EI
When an interrupt request is output with the EI
the interrupt sequence is activated, respectively. When the EI
2
EI OS enable bit (ISE) is cleared to "0". When no peripheral resource has the EI
set the EI
cleared to "0" at a reset.
❍ Setting the Extended Intelligent I/O service (EI
2
The EI OS descriptor addressing bits (ICS3 to ICS0) are enabled for a write. Used to set the
2
EI OS descriptor address. The EI
addressing bits (ICS3 to ICS0) to the address value. The EI
(ICS3 to ICS0) are initialized to "0000
Table 3.3-3 "Interrupt control registers (ICR00 to ICR15) bit configuration" shows the
relationships between interrupt level setting bits and individual interrupt levels.
IL1
0
0
1
1
0
0
1
1
2
OS) enable bit (ISE)
2
OS enable bit (ISE) to "0" by means of software.The EI
2
IL0 Interrupt level
0
0 (Highest interrupt)
1
0
1
0
1
6 (Lowest interrupt)
0
1 7 (No interrupt)
2
OS enable bit (ISE) set to "1" or to "0", EI
2
OS) descriptor address
OS descriptor is addressed by setting the EI
" at a reset. Initialized to level 7 (no interrupt) at a reset.
B
CHAPTER 3 INTERRUPT
2
OS process is completed, the
2
OS feature,
2
OS enable bit (ISE) is
2
OS descriptor
2
OS descriptor addressing bits
2
OS or
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