Fujitsu F2MC-16LX Hardware Manual page 541

Figure B.4-2 Example of register indirect addressing with post increment
MOVW A, @RW1+
Before execution
After execution
❍ Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to
3)
Memory is accessed using the address obtained by adding an offset to the contents of general-
purpose register RWj. Two types of offset, byte and word offsets, are used. They are added as
signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB)
when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank
register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or
RW6 is used.
Figure B.4-3 Example of register indirect addressing with offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H
Before execution
After execution
❍ Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset
to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a
signed numeric value.
Figure B.4-4 Example of long register indirect addressing with offset
MOVW A, @RL2+25H
Before execution
After execution
(@RWj+ j = 0 to 3)
(This instruction reads data by register indirect addressing with post
increment and stores it in A.)
A 0 7 1 6 2 5 3 4
RW1 D 3 0 F DTB 7 8
A 2 5 3 4 F F E E
RW1 D 3 1 1 DTB 7 8
(This instruction reads data by register indirect addressing with an
offset and stores it in A.)
A 0 7 1 6 2 5 3 4
RW1 D 3 0 F DTB 7 8
A 2 5 3 4 F F E E
RW1 D 3 0 F DTB 7 8
(@RLi + disp8 i = 0 to 3)
(This instruction reads data by long register indirect addressing with an
offset and stores it in A.)
A 0 7 1 6 2 5 3 4
RL2 F 3 8 2 4 B 0 2
A 2 5 3 4 F F E E
RL2 F 3 8 2 4 B 0 2
APPENDIX B Instructions
Memory space
78D310H F F
78D30FH E E
Memory space
78D320H F F
E E
78D31FH
(+10H)
Memory space
824B28H F F
824B27H E E
(+25H)
525