Fujitsu F2MC-16LX Hardware Manual page 253

I List of input capture registers
Figure 12.2-14 "Input capture registers" shows a list of the input capture registers.
15
00005D
H
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Input capture data register
00005F
H
(R)
00005C
H
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 Input capture data register
00005E
H
(R)
000060 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Control status register
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000
I Input capture data register (IPCP0, 1)
The input capture data register (IPCP0, 1) has the bit configuration shown below.
Figure 12.2-15 Bit configuration of input capture data register (IPCP0, 1)
15
00005D
H
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Input capture data register
00005F
H
(R)
00005C
H
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 Input capture data register
00005E
H
(R)
The input capture data register (IPCP0, 1) is a register containing the 16-bit free-running timer
value when a valid edge of the external pin input waveform is detected.
This register uses word access. Writing to this register is not permitted.
Figure 12.2-14 Input capture registers
14 13 12
(R) (R) (R)
7 6 5 4
(R) (R) (R)
7 6 5 4
14 13 12
(R) (R) (R)
7 6 5 4
(R) (R) (R)
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
11 10 9 8
(R) (R) (R) (R)
3 2 1 0
(R) (R) (R) (R)
3 2 1 0
11 10 9 8
(R) (R) (R) (R)
3 2 1 0
(R) (R) (R) (R)
IPCP0, 1
Initial value XXXXXXXX
IPCP0, 1
Initial value XXXXXXXX
ICS01
B
IPCP0, 1
Initial value XXXXXXXX
IPCP0, 1
Initial value XXXXXXXX
B
B
B
B
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