Communication Prescaler Control Register (Cdcr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 21 UART

21.2.5 Communication Prescaler Control Register (CDCR)

This section describes the configuration and functions of the communication
prescaler control register (CDCR).
I Communication prescaler control register (CDCR)
The bit configuration of the communication prescaler control register (CDCR) is illustrated
below.
15
000025 MD SRST
H
(R/W) (R/W)
(0)
The UART operation clocks are obtained by dividing the machine clock. The converter is
designed so that constant baud rates with respect to various machine clocks are obtained
through the communication prescaler. The CDCR is a register that controls machine clock
division.
[Bit 15] MD: Machine clock divide moDe select
This bit is used to enables operation of the communication prescaler.
0
1
[Bits 14] SRST: Set ReSeT
This bit resets all operations of the UART. It initializes all data and register values.
0
1
Note:
Setting this bit will forcibly clear all data and register values. All setting values will return to
their initial values. Data being transferred as well as saved data will be invalid until the
respective settings have been made again.
404
14 13 12 11
- - DIV3 DIV2 DIV1 DIV0
(-) (-) (R/W) (R/W) (R/W) (R/W) Reading/writing
(0) (-) (-) (0)
The communication prescaler stops.
The communication prescaler operates.
Initial value (has no effect)
Forced reset
10 9 8 Communication prescaler
control register (CDCR)
(0) (0) (0) Initial value