Fujitsu F2MC-16LX Hardware Manual page 525

Table A-2 I/O Map (Continued)
Address
56 Output compare control register (ch0)
H
57 Output compare control register (ch1)
H
58 Output compare control register (ch2)
H
59 Output compare control register (ch3)
H
5A Output compare control register (ch4)
H
5B Output compare control register (ch5)
H
5C Input capture register (ch0) lower
H
5D Input capture register (ch0) upper
H
5E Input capture register (ch1) lower
H
5F Input capture register (ch1) upper
H
60 Input capture control register
H
61
H
62 Timer data register lower
H
63 Timer data register upper
H
64 Timer control status register
H
65 Timer control status register
H
66 Compare clear register lower
H
67 Compare clear register upper
H
68 Up/down count register ch0
H
69 Up/down count register ch1
H
6A Reload compare register ch0
H
6B Reload compare register ch1
H
6C Counter control register lower ch0
H
6D Counter control register upper ch0
H
6E
H
6F ROM mirror function select register
H
70 Counter control register lower ch1
H
71 Counter control register upper ch1
H
72 Count status register ch0
H
73
H
74 Count status register ch1
H
Register Abbreviation Access
OCS0 R/W
OCS1 R/W
OCS2 R/W
OCS3 R/W
OCS4 R/W
OCS5 R/W
R
IPCP0
R
R
IPCP1
R
ICS01 R/W
Reserved area
TCDT R/W
TCDT R/W
TCCS R/W
TCCS R/W
CPCLR R/W
UDCR0 R
UDCR1 R
RCR0 W
RCR1 W
CCRL0 R/W
CCRH0 R/W
Reserved area
ROMM W
CCRL1 R/W
CCRH1 R/W
CSR0 R/W
Reserved area
CSR1 R/W
APPENDIX A Memory Map
Resource Initial value
0000--00
---00000
16-bit output timer
0000--00
output compare
---00000
(ch0-5)
0000--00
---00000
XXXXXXXX
XXXXXXXX
16-bit output timer
input capture XXXXXXXX
(ch0, 1)
XXXXXXXX
00000000
00000000
00000000
00000000
16-bit output timer
free-run timer
0--00000
XXXXXXXX
XXXXXXXX
00000000
00000000
00000000
8/16-bit up/down
timer counter
00000000
0X00X000
00000000
ROM mirror
-------1
function
0X00X000
8/16-bit up/down
-0000000
timer counter
00000000
8/16-bit UDC 00000000
509