Data Registers (Adcr2 And Adcr1) - Fujitsu F2MC-16LX Hardware Manual

19.2.3 Data Registers (ADCR2 and ADCR1)

The bit configurations and functions of the data registers (ADCR2 and ADCR1) are
explained below.
I Data registers (ADCR2 and ADCR1)
The function of each bit of the data registers (ADCR2 and ADCR1) is described below.
ADCR1
Address: 000048
ADCR2
Address: 000049
The data registers (ADCR2 and ADCR1) are registers for storing conversion results as digital
values. The upper two bits of conversion values are stored in ADCR2, while the lower eight bits
are stored in ADCR1. The values of these registers are updated at the end of each conversion.
Normally, the last conversion value is stored. The S10-bits must be rewritten if A/D operation
stops before conversion ends. Rewriting after conversion may result in an undefined ADCR
data. To read ADCR with 10-bit mode specified, always use a word move instruction. The
ADCR registers have a conversion data protection function. Refer to Section 19.4 "Conversion
Data Protection Function".
Do not write data to these registers during A/D operation. When S10 is set to "0", conversion
results will be output in units of ten bits; when S10 is set to "1", conversion results will be output
in units of eight bits.
ST1
0
0
1
1
Note 1: Setting ST1 and ST0 = 00 or CT1 and CT0 = 00 when operating at
20MHz will sometimes prevent the proper analog voltages from being
obtained.
bit 7 6 5
D7 D6 D5
H
X X X
R R R
bit 15 14 13
S10 ST1 ST0 CT1
H
0 0 0
W W W
Sampling time
ST0
setting bit
20 machine cycles
0
(1.0 µS@20MHz)
32 machine cycles
1
(1.6 µS@20MHz)
48 machine cycles
0
(2.4 µS@20MHz)
128 machine cycles
1
(6.4 µS@20MHz)
CHAPTER 19 8/10-BIT A/D CONVERTER
4 3 2 1
D4 D3 D2 D1
X X X X
R R R R
12 11 10 9
CT0 - D9
0 0 X X
W W R R
CT1 CT0
44 machine cycles
0 0
(2.2 µS@20MHz)
66 machine cycles
0 1
(3.3 µS@20MHz)
88 machine cycles
1 0
(4.4 µS@20MHz)
176 machine cycles
1 1
(8.8 µS@20MHz)
0
D0
X Initial value
R Read/write
8
D8
X Initial value
R Read/write
Compare time
setting bit
365