Fujitsu F2MC-16LX Hardware Manual page 295

[Bit 11] OVIR (timer overflow interrupt request flag)
This bit is a flag used to indicate an overflow of the 16-bit up-count timer to the area from
FFFF to 0000 . If this bit is set when timer overflow interrupt requests are enabled (bit
H H
10:OVIE = "1"), a timer overflow interrupt request is generated.
OVIR
Cause for setting Set if a timer overflow occurs (to the area from FFFF
Writing "0" or clearing by µDMAC
Cause of clearing
• Initialized to "0" at reset
• Reading and writing are allowed; however, only writing "0" is effective, while writing "1"
causes no changes in the bit value.
• Read-modify-write type instructions return "1" irrespective of bit values.
[Bit 10] OVIE (timer overflow interrupt request enable)
This bit is used for control of measurement end interrupt requests during pulse width
measurement, as shown in the following table.
OVIE
Overflow interrupt request output prohibited (No interrupts occur even if OVIR is
0
set) [initial value]
1 Overflow interrupt request output allowed (An interrupt occurs if OVIE is set)
• Initialized to "0" at reset.
• Reading and writing are allowed.
[Bit 9] ERR (Error Flag)
This bit is a flag that indicates that, in the repeated measurement mode of pulse width
measurement, a measurement operation has completed before the previous measurement
result was read out from the PWCR. In this case, the PWCR value will be updated to the
new measurement result while the immediately previous measurement result will be lost.
Measurement will continue irrespective of the value of this bit.
ERR
This bit is set if a measurement result that has not been read out is
Cause for setting
overwritten by the next result.
Cause of clearing This bit is cleared whenever the PWCR (measurement result) is read
• Initialized to "0" at reset.
• Only reading is allowed. Write operations have no effect.
[Bit 8] Reserved bit
This bit is reserved.
CHAPTER 14 PWC TIMER
Cause of setting or clearing
Operation
Cause of setting or clearing
to 0000 )
H H
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