Fujitsu F2MC-16LX Hardware Manual page 411

I UART block diagram
Figure 21.1-1 "Block diagram of the UART" shows a block diagram of the UART.
Control signal
Dedicated baud
rate generator
PPG1
(internal connection)
External clock
SIN0
Reception state
detection circuit
SMR
register
Figure 21.1-1 Block diagram of the UART
Clock
selector
Reception
circuit
clock
Reception control
circuit
Start-bit
detector
circuit
Reception
bit counter
Reception
parity
counter
Reception
shifter
Reception
DMAC reception
control circuit
error transmission
signal (to CPU)
SIDR
2
F MC-16LX BUS
MD1
MD0
CS2
CS1
SCR
CS0
register
SCKE
SOE
Reception interrupt (to CPU)
SCK0
Transmission clock
Send interrupt (to CPU)
Transmission
control circuit
Transmission
start circuit
Transmission
bit counter
Transmission
parity counter
SOT0
Transmission
shifter
Transmission
start
SODR
PEN PE
P ORE
SBL FRE
CL RDRF
SSR
A/D TDRE
register
REC BDS
REX RIE
TXE TIE
CHAPTER 21 UART
Control signal
395