Fujitsu F2MC-16LX Hardware Manual page 223

Table 10.2-1 Function of bits in watchdog timer control register (WDTC)
Bit name
Bit 7 PONR
Bit 5 WRST Reset cause
Bit 4 ERST bits
Bit 3 SRST
Bit 6 Reserved Reserved bit
Watchdog
Bit 2 WTE
control bit
Bit 1 WT1 Interval time
Bit 0 WT0 selection bits
• These are read-only bits that indicate reset causes. Each of these
bits is set to "1" when the corresponding reset cause has occurred.
• All of these bits are cleared to "0" after reading of the WDTC register.
• When power is turned on, the contents of bits other than the PONR
bit are not assured. Therefore, if the POBR bit is set to "1", ignore the
contents of other bits.
Reading and writing to this bit has no effect on operation.
• When "0" is written to this bit, the watchdog timer is started (at the
first write event after a reset) or the 2-bit counter is cleared (at the
second and succeeding write events after a reset).
• Writing "1" does not affect operation.
• These are the bits for selecting the interval time of the watchdog
timer.
• The interval time varies, as shown in Figure 10.2-1 "Watchdog timer
control register (WDTC)", between the case where the sub-clock
mode is selected as the clock mode (the sub-clock display bit (SCM)
of the clock selection register (CKSCR) is "0") or the clock source of
the watchdog timer is set to the watch timer by the watch timer
control register (WTC) (the watchdog timer clock source selection bit
(WDCS) is set to "0") and the case where the main clock mode or
PLL clock mode is selected as the clock mode while the WDCS bit of
WTC is set to "1".
• Only data that has been defined before the start of the watchdog
timer are effective.
Any data that is written after the start of the watchdog timer is
ignored.
• These bits are write-only.
CHAPTER 10 WATCHDOG TIMER
Function
207