Fujitsu F2MC-16LX Hardware Manual page 353

[Bit 12] PIE1: ppg Interrupt Enable (PPG interrupt enable)
This bit is used to prohibit or allow PPG interrupts.
PIE0
0 Interrupts prohibited
1 Interrupts allowed
If PUF0 is set to "1" when this bit is"1", an interrupt request is generated. When this bit is "0", no
interrupts are generated.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[Bit 11] PUF1: ppg Underflow Flag (PPG counter underflow)
This bit is used to indicate the result of PPG counter underflow detection.
PUF0
0 No PPG counter underflow detected
1 PPG counter underflow detected
In 8-bit PPG6 channel mode (PPG0/1,PPG2/3,PPG4/5) and 8-bit prescaler + 8-bit PPG mode,
this bit is set to "1" when an underflow occurs because the counter value of channel 1, 3, 5
changes from 00 to FF
H
PPG5), this bit is set to "1" when an underflow occurs because the counter value of channel 1,
3, 5 or channel 0, 2, 4 changes from 0000
"1" has no effect. Read-modify-write type instructions will always return "1".
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
Operation state
Operation state
. In 16-bit PPG3 channel mode (PPG0/PPG1, PPG2/PPG3, PPG4/
H
to FFFF
H
CHAPTER 17 8/16-BIT PPG TIMER
. Writing "0" clears this bit to "0". Writing
H
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