Serial Mode Control Status Register (Smcs) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 20 EXPANDED I/O SERIAL INTERFACE

20.2.1 Serial Mode Control Status Register (SMCS)

This section describes the configuration and functions of the serial mode control
status register (SMCS).
I Serial mode control status register (SMCS)
The serial mode control status register (SMCS) controls the data transfer mode of serial I/O
operations.
The bit configuration of the serial mode control status register (SMCS) is illustrated below.
SMCS
address: 000027
00002B
SMCS
address: 000026
00002A
The functions of the bits of the serial mode control status register (SMCS) are described below.
[Bits 15, 14, 13] SMD2, SMD1 and SMD0: Serial Shift Clock Mode (Shift clock select)
These bits select the serial shift clock mode. Table 20.2-1 "Settings of serial shift clock
mode" shows the settings for the serial shift clock mode.
Table 20.2-1 Settings of serial shift clock mode
Select the serial shift clock mode as follows:
SMD2 SMD1 SMD0
0
0
0
0
1
1
1
1
380
15 14 13
SMD2 SMD1 SMD0 SIE
H
H
R/W R/W R/W R/W R/W
7 6 5
- - -
H
H
Note 1: Only "0" can be written
Note 2: Only "1" can be written. Reading always returns "0."
φ=16MHz φ=8MHz φ=4MHz
div=8 div=4
0 0
1MHz 1MHz 500KHz
0 1
500KHz 500KHz 250KHz
1 0
125KHz 125KHz 62.5KHz
62.5KHz 62.5KHz 31.2KHz
1 1
31.2KHz 31.2KHz 15.6KHz
0 0
External shift clock mode
0 1
reserved
1 0
1 1 reserved
12 11 10 9
SIR BUSY STOP STRT 00000010
R/W R/W R/W
↑
Note 1
4 3 2 1
- MODE BDS SOE SCOE ----0000
R/W R/W R/W R/W
Setting of communication prescaler (SDCR)
Division
Div
factor
div=4 MD DIV3 DIV2 D1IV DIV0
1 1
2
2 1
4
3 1
16
4 1
32
5 1
64
6 1
7 1
8 1
8 Initial value
B
↑
Note 2
0 Initial value
B
Recommended
(Machine clock)
machine clock
speed
0 0 0 0 2MHz
0 0 0 1 4MHz
0 0 1 0 6MHz
0 0 1 1 8MHz
0 1 0 0 10MHz
0 1 0 1 12MHz
0 1 1 0 14MHz
0 1 1 1 16MHz