Fujitsu F2MC-16LX Hardware Manual page 524

APPENDIX
Table A-2 I/O Map (Continued)
Address
PPG0 operation mode control
3A
H
PPG1 operation mode control
3B
H
PPG2 operation mode control
3C
H
PPG3 operation mode control
3D
H
PPG4 operation mode control
3E
H
PPG5 operation mode control
3F
H
40 PPG0, 1 output control register
H
41
H
42 PPG2, 3 output control register
H
43
H
44 PPG4, 5 output control register
H
45
H
46
H
Control status register
47
H
48
H
49
H
4A Output compare register (ch0) lower
H
4B Output compare register (ch0) upper
H
4C Output compare register (ch1) lower
H
4D Output compare register (ch1) upper
H
4E Output compare register (ch2) lower
H
4F Output compare register (ch2) upper
H
50 Output compare register (ch3) lower
H
51 Output compare register (ch3) upper
H
52 Output compare register (ch4) lower
H
53 Output compare register (ch4) upper
H
54 Output compare register (ch5) lower
H
55 Output compare register (ch5) upper
H
508
Register
register
register
register
register
register
register
Data register
Abbreviation Access
PPGC0 R/W
PPGC1 R/W
PPGC2 R/W
PPGC3 R/W
PPGC4 R/W
PPGC5 R/W
PPG01 R/W
Reserved area
PPG23 R/W
Reserved area
PPG45 R/W
Reserved area
ADCS1 R/W
ADCS2 R/W
ADCR1 R
ADCR2 R
OCCP0 R/W
OCCP1 R/W
OCCP2 R/W
OCCP3 R/W
OCCP4 R/W
OCCP5 R/W
Resource Initial value
0X000XX1
0X000001
0X000XX1
8/16-bit PPG
(ch0-5)
0X000001
0X000XX1
0X000001
8/16-bit PPG 00000000
8/16-bit PPG 00000000
8/16-bit PPG 00000000
00000000
00000000
A/D converter
XXXXXXXX
00000XXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
16-bit output timer
XXXXXXXX
output compare
XXXXXXXX
(ch0-5)
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX