Block Diagram Of The 8/16-Bit Ppg Timer - Fujitsu F2MC-16LX Hardware Manual

17.1.1 Block Diagram of the 8/16-Bit PPG Timer

Block diagrams of channels 0/2/4 and channels 1/3/5 of the 8/16-bit PPG timer are
shown below.
I Block diagram of the 8/16-bit PPG timer
Figure 17.1-1 "Block diagram of the 8/16-bit PPG timer (channels 0/2/4)" shows a block diagram
of channels 0,2, and 4. Figure 17.1-2 "Block diagram of the 8/16-bit PPG timer (channels 1/3/5)"
shows a block diagram of channels 1,3, and 5.
Figure 17.1-1 Block diagram of the 8/16-bit PPG timer (channels 0/2/4)
Peripheral clock: divide-by-16
Peripheral clock: divide-by-8
Peripheral clock: divide-by-4
Peripheral clock: divide-by-2
Peripheral clock
Timebase counter output
Main clock: divide-by-512
L/H select
PCNT(down-counter)
L/H selector
Count clock
select
PRLL
PRLL
PPG0/2/4 output allowed
PPG0/2/4 output latch
PEN0
PUF0
PRLBH
(operation mode control)
CHAPTER 17 8/16-BIT PPG TIMER
PPG0/2/4
A/D converter
S
R Q
IRQ
ch1/3/5 borrow
PIE0
PPGC0
L data bus
H data bus
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