Fujitsu F2MC-16LX Hardware Manual page 472

CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION
I Functions of Detect Address Setting Registers
• There are two detect address setting registers (PADR0 and PADR1) that consist of a high
byte (bank), middle byte, and low byte, totaling 24 bits.
Table 24.3-2 Address Setting of Detect Address Setting Registers
Register Name
Detect address
setting
register 0 (PADR0)
Detect address
setting
register 1 (PADR1)
• In the detect address setting registers (PADR0 and PADR1), starting address (first byte) of
instruction to be replaced by INT9 instruction should be set.
Figure 24.3-4 Setting of Starting Address of Instruction Code to be Replaced by INT9
Address Instruction code
FF001C :
FF001F :
FF0022 :
Notes: • When an address of other than the first byte is set to the detect address setting register
(PADR0 and PADR1), the instruction code is not replaced by INT9 instruction and a
program of an interrupt processing is not be performed. When the address is set to the
second byte or subsequent, the address set by the instruction code is replaced by "01"
(INT9 instruction code) and, which may cause malfunction.
• The detect address setting registers (PADR0 and PADR1) should be set after disabling the
address match detection (PACSR: AD0E = 0 or AD1E = 0) of corresponding address match
control registers. If the detect address setting registers are changed without disabling the
address match detection, the address match detection function will work immediately after
an address match occurs during writing address, which may cause malfunction.
• The address match detection function can be used only for addresses of the internal ROM
area. If addresses of the external memory area are set, the address match detection
function will not work and the INT9 instruction will not be executed.
456
Interrupt Output
Enable
PACSR: AD0E
PACSR: AD1E
Set to detect address (High : FF
Mnemonic
A8 00 00 MOVW
4A 00 00 MOVW
4A 80 08 MOVW
Address Setting
High Set the upper 8 bits of detect address 0 (bank).
Middle Set the middle 8 bits of detect address 0.
Low Set the lower 8 bits of detect address 0.
High Set the upper 8 bits of detect address 1 (bank).
Middle Set the middle 8 bits of detect address 1.
Low Set the lower 8 bits of detect address 1.
, Middle : 00
H
RW0, #0000
A, #0000
A,#0880
, Low : 1F )
H H