Fujitsu F2MC-16LX Hardware Manual page 542

APPENDIX
❍ Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The
offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB).
Note that the operand address of each of the following instructions is not deemed to be (next
instruction address + disp16):
• DBNZ eam, rel
• DWBNZ eam, rel
• CBNE eam, #imm8, rel
• CWBNE eam, #imm16, rel
• MOV eam, #imm8
• MOVW eam, #imm16
Figure B.4-5 Example of program counter indirect addressing with offset (@PC + disp16)
❍ Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of
general-purpose register RW7. Address bits 16 to 23 are indicated by the data bank register
(DTB).
526
MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with a
offset and stores it in A.)
Before execution
After execution
Figure B.4-6 Example of register indirect addressing with base index
(@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a
base index and stores it in A.)
Before execution
After execution
A 0 7 1 6 2 5 3 4
PCB C 5 PC 4 5 5 6
A 2 5 3 4 F F E E
+20H
+4
PCB C 5 PC 4 5 5 A
A 0 7 1 6 2 5 3 4
RW1 D 3 0 F DTB 7 8
+
RW7 0 1 0 1
A 2 5 3 4 F F E E
RW1 D 3 0 F DTB 7 8
RW7 0 1 0 1
Memory space
C5457BH F F
C5457AH E E
C5455AH
C54559H 0 0
MOVW
C54558H 2 0
A, @PC+20H
C54557H 9 E
C54556H 7 3
Memory space
78D411H F F
78D410H E E