Serial Mode Register (Smr) - Fujitsu F2MC-16LX Hardware Manual

21.2.1 Serial Mode Register (SMR)

This section describes the configuration and functions of the serial mode register.
I Serial mode register (SMR)
The bit configuration of the serial mode register (SMR) is illustrated below.
7
000020 MD1 MD0 CS2 CS1 CS0
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing
(0)
The functions of the bits of the serial mode register (SMR) are as follows.
[Bits 7, 6] MD1, MD0: Mode Select
These bits are used to select the UART operation mode.
Mode
0
1
2
-
In Mode 1, the CLK asynchronous mode (multiprocessor mode), several slave CPUs are
connected to one host CPU. The MB90470 cannot distinguish the data format of reception
data; therefore, it supports only the master in multiprocessor mode. The parity check function
cannot be used. Set the PEN bit of the SCR Register to "0".
[Bits 5, 4, 3] CS2, CS1, CS0: Clock Select
These bits select the baud rate clock sources. When a dedicated baud rate generator is
selected, the baud rate will be determined at the same time.
CS2 to 0
000
B
110
111
• PPG1 will be selected in the MB90470 if an internal clock is selected.
• The use of the clock division ratio 1/1 (CS-CS0 = 000B) during synchronous transfer is
prohibited.
[Bit 2] not used
This bit is not used.
6 5 4
(0) (0) (0)
MD1 MD0
0 0 Asynchronous (start-stop) normal mode
0 1 Asynchronous (start-stop) multiprocessor mode
1 0 CLK synchronous mode
1 1 Setting prohibited
Clock input
to 101 Dedicated baud rate generator
B
Internal clock
B
External clock
B
3 2 1 0
SCKE SOE
Reserved
(0) (X) (0) (0)
Operation mode
CHAPTER 21 UART
Serial mode register (SMR)
Initial value
397