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Fujitsu F2MC-8L Series Hardware Manual

Fujitsu F2MC-8L Series Hardware Manual

8-bit microcontroller
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  • Page 1 The following document contains information on Cypress products.
  • Page 2 FUJITSU SEMICONDUCTOR CM25-10111-3E CONTROLLER MANUAL MC-8L 8-BIT MICROCONTROLLER MB89120/120A SERIES HARDWARE MANUAL...
  • Page 4 MC-8L 8-BIT MICROCONTROLLER MB89120/120A SERIES HARDWARE MANUAL FUJITSU LIMITED...
  • Page 6 F MC(R)-8L MB89600 Series Programming Manual. Trademarks MC(R) is an acronym for Fujitsu Flexible Microcontroller and is a registered trademark of Fujitsu Limited. Structure of This Manual This manual consists of the following 14 chapters: Chapter 1 Overview This chapter describes the features and basic specifications of the MB89120/120A Series.
  • Page 7 Chapter 10 External Interrupt Circuit 1 (Edge) This chapter describes the functions and operation of the external interrupt circuit 1 (edge) of the MB89120/120A Series. Chapter 11 External Interrupt Circuit 2 (Level) This chapter describes the functions and operation of the external interrupt circuit 2 (Level) of the MB89120/120A Series.
  • Page 8 2. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.
  • Page 9 READING THIS MANUAL Page Layout Each section is organized on a page or on facing pages so that the contents of each section can be viewed without turning pages. The contents of each section are summarized immediately below the title. A rough overview of this product can be obtained by reading through these summaries.
  • Page 10 Interrupt is accepted when interrupt is enabled (CCR:I=1). Current status Bit abbreviation Register abbreviation Example of a description of a shared terminal P25/SCK terminal Some terminals can share several functions by switching in the program setting. function names of shared terminal are separated by "/."...
  • Page 11 Structure of facing pages and description rules of this manual ubtitle Summary of the section Section title Chapter title Upper section Table title Reference : igure title Indicates the manual or item to be referenced. Tip : Describes helpful and convenient information. Check : Indicates items to be noted.
  • Page 12 Materials required for development and development tools The following items are required for developing our product. For the required materials and development tools, contact a Fujitsu salesperson. Required manuals for development Check column MC-8L MB89120/120A series Datasheet (Describes electrical characteristics and examples of our products.)
  • Page 13 Required items for evaluating one-time PROM and EPROM microcomputer (When writing by the user) Check column MB89P131, MB89P133A, or MB89P135A ROM writer (a writer that can be used for writing MBM27C256A) Refer to the datasheet for the recommended writer. Package conversion adopter for writing (Purchase from Sunhayato Corporation) Package Socket product number...

  • Page 14: Table Of Contents

    CONTENTS CHAPTER 1 OVERVIEW ....................1 MB89120/120A Series Features ......................2 MB89120/120A Series Product Lineup ....................4 Differences among Products ......................... 6 MB89120/120A Series Block Diagram ....................8 Pin Assignment ............................9 Package Dimensions ........................... 12 Pin Functions ............................15 I/O Circuit Types ..........................
  • Page 15 3.7.6 State Transition Diagram 1 (Product with Power-on Reset Function in Dual-clock Configuration) 83 3.7.7 State Transition Diagram 2 (Product without Power-on Reset Function in Dual-clock Configuration) ..........................86 3.7.8 State Transition Diagram 3 (Products in Single-clock Configuration) ..........89 3.7.9 Pin States in Standby Modes ......................
  • Page 16 8/16-bit Timer/Counter Registers ....................... 165 7.4.1 Timer Control 1 Register (T1CR) ....................166 7.4.2 Timer Control 2 Register (T2CR) ....................169 7.4.3 Timer 1 Data Register (T1DR) ...................... 171 7.4.4 Timer 2 Data Register (T2DR) ...................... 173 8/16-bit Timer/Counter Interrupts ....................... 175 Operation of Interval Timer Function ....................
  • Page 17 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) ........245 11.1 Overview of External Interrupt Circuit 2 (Level) ................246 11.2 Structure of External Interrupt Circuit 2 ..................... 247 11.3 External Interrupt Circuit 2 Pins ......................249 11.4 External Interrupt Circuit 2 Registers ....................251 11.4.1 External Interrupt 2 Control Register (EIC2) ................
  • Page 18 Programming One-time PROM ....................... 329 Programming EPROM with Piggyback/Evaluation Device .............. 334 APPENDIX E MB89120 Series Pin States ....................336 INDEX ..........................339 xiii...
  • Page 19 FIGURES Figure 1.4-1 MB89120/120A Series Block Diagram ..................8 Figure 1.5-1 FTP-48P-M13 Pin Assignment ....................9 Figure 1.5-2 DIP-48P-M01 Pin Assignment ....................10 Figure 1.5-3 MQP-48C-P01 Pin Assignment ....................11 Figure 1.6-1 FPT-48P-M13 Package Dimensions ..................12 Figure 1.6-2 DIP-48P-M01 Package Dimensions ..................13 Figure 1.6-3 MQP-48C-P01 Package Dimensions ..................
  • Page 20 Figure 3.7-4 State Transition Diagram 3 (Product with Power-on Reset Function) ........89 Figure 3.7-5 State Transition Diagram 3 (Product without Power-on Reset Function) ........89 Figure 3.8-1 Mode Data Structure ......................... 95 Figure 3.8-2 Memory Access Selection Operation ..................96 Figure 4.2-1 Block Diagram of Port 0 Pin ....................
  • Page 21 Figure 7.11-2 Error on Starting Counter Operation ..................188 Figure 8.2-1 Block Diagram of 8-bit Serial I/O .................... 195 Figure 8.3-1 Block Diagram of 8-bit Serial I/O Pins ..................198 Figure 8.4-1 8-bit Serial I/O-1 Registers ..................... 199 Figure 8.4-2 Serial Mode Register (SMR) ....................
  • Page 22 Figure 11.6-2 Operation of External Interrupt Circuit 2 (INT20) ..............257 Figure 12.2-1 Block Diagram of Watch Prescaler ..................264 Figure 12.3-1 Watch Prescaler Control Register (WPCR) ................266 Figure 12.5-1 Interval Timer Function Settings ....................269 Figure 12.5-2 Watch Prescaler Operation ..................... 270 Figure 12.6-1 Effect of Clearing Watch Prescaler on Buzzer Output .............
  • Page 23 Figure D.1-1 Memory Map in PROM Mode (MB89P131) ................330 Figure D.1-2 Memory Map in PROM Mode (MB89P133A) ................330 Figure D.1-3 Memory Map in PROM Mode (MB89P135A) ................331 Figure D.1-4 Screening Flowchart ....................... 333 Figure D.2-1 Memory Map of Piggyback/Evaluation Device ............... 334 xviii...
  • Page 24 TABLES Table 1.2-1 MB89120/120A Series Product Lineup ..................4 Table 1.2-2 CPU and Peripheral Functions for MB89120/120A Series ............4 Table 1.3-1 Package and Corresponding Products ..................6 Table 1.7-1 Pin Description ......................... 15 Table 1.7-2 Pin Description for External EPROM Pins (MB89PV130A only) ..........16 Table 1.8-1 I/O Circuit Type .........................
  • Page 25 Table 4.2-3 Port 0 Register Functions ...................... 103 Table 4.2-4 Port 0 Pin States ........................106 Table 4.3-1 Port 1 Pins ..........................107 Table 4.3-2 Correspondence between Pins and Registers for Port 1 ............108 Table 4.3-3 Port 1 Register Functions ...................... 109 Table 4.3-4 Port 1 Pin States ........................
  • Page 26 Table 10.3-1 External Interrupt Circuit 1 Pins ....................233 Table 10.4-1 External Interrupt 1 Control Register 1 (EIC1) Bits ..............237 Table 10.4-2 External Interrupt 1 Control Register 2 (EIC2) Bits ..............238 Table 10.5-1 Register and Vector Table for External Interrupt Circuit 1 Interrupts ........240 Table 11.3-1 Terminals related to External Interrupt Circuit 2 Pins .............
  • Page 27 Table E-1 Pin States in Each Mode ......................336 xxii...

  • Page 28: Chapter 1 Overview

    CHAPTER 1 OVERVIEW This chapter describes the features and basic specifications of the MB89120/120A series. 1.1 MB89120/120A Series Features 1.2 MB89120/120A Series Product Lineup 1.3 Differences among Products 1.4 MB89120/120A Series Block Diagram 1.5 Pin Assignment 1.6 Package Dimensions 1.7 Pin Functions 1.8 I/O Circuit Types...

  • Page 29: Mb89120/120A Series Features

    CHAPTER 1 OVERVIEW MB89120/120A Series Features The MB89120/120A series are single-chip general-purpose microcontrollers. The microcontrollers contain a variety of peripheral functions such as timers, serial interfaces, an A/D converter, and an external interrupt as well as a compact instruction set. MB89120/120A Series Features High-speed processing at low voltage Minimum execution time: 0.95 µs (at 4.2 MHz source oscillation)
  • Page 30 1.1 MB89120/120A Series Features Eight inputs are available also for wake-up from low-power consumption mode (with the L- level detection function). Low-power consumption (standby modes) • Stop mode (Oscillation stops to minimize the current consumption.) • Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) •...

  • Page 31: Mb89120/120A Series Product Lineup

    CHAPTER 1 OVERVIEW MB89120/120A Series Product Lineup The MB89120/120A series contains 7 types of products. Table 1.2-1 lists the product lineup and Table 1.2-2 lists the CPU and periperal functions. MB89120/120A Series Product Lineup Table 1.2-1 MB89120/120A Series Product Lineup Part number Parameter MB89121...
  • Page 32 1.2 MB89120/120A Series Product Lineup Table 1.2-2 CPU and Peripheral Functions for MB89120/120A Series Part number Parameter MB89121 MB89123A MB89125A MB89P133A MB89P131 MB89P135A MB89PV130A Output-only ports (N-ch open-drain): 4 (All also serve as peripherals.) Output-only ports (CMOS): Ports General-purpose I/O ports (CMOS):) 24 (All also serve as peripherals.

  • Page 33: Differences Among Products

    CHAPTER 1 OVERVIEW Differences among Products This section describes the differences between the 5 products in the MB89120/120A series and lists points to note in product selection. Differences among Products and Points to Note for Product Selection Table 1.3-1 Package and Corresponding Products Package MB89121 MB89123A...
  • Page 34 1.3 Differences among Products Mask options Functions that can be selected as options and how to designate these options vary by the product. Before using options, check Appendix C, "Mask Options." Take particular care on the following points: • A pull-up resistor cannot be set for P40 to P43 when using the AD converter. Specify "none" for all the pull-up resistors of P40 to P43 when using the AD converter with MB89P131 or MB89P133A.

  • Page 35: Mb89120/120A Series Block Diagram

    CHAPTER 1 OVERVIEW MB89120/120A Series Block Diagram Figure 1.4-1 shows the block diagram of the MB89120/120A series. MB89120/120A Series Block Diagram Figure 1.4-1 MB89120/120A Series Block Diagram Main clock Oscillator Timebase (at 4.2 MHz max.) timer Reset circuit Clock controller (Watchdog timer) Sub clock Low-power...

  • Page 36: Pin Assignment

    1.5 Pin Assignment Pin Assignment Figures 1.5-1 to 1.5-3 show the pin assignment diagrams for the MB89120/120A series. FTP-48P-M13 Pin Assignment Figure 1.5-1 FTP-48P-M13 Pin Assignment (Top view) P36/INT2 P37/BZ/ (RCO) MOD0 P00/ (INT20) MOD1 P01/ (INT21) P02/ (INT22) P03/ (INT23) P04/ (INT24) P05/ (INT25) P06/ (INT26)

  • Page 37: Figure 1.5-2 Dip-48P-M01 Pin Assignment

    CHAPTER 1 OVERVIEW DIP-48P-M01 Pin Assignment Figure 1.5-2 DIP-48P-M01 Pin Assignment (Top View) P07/(INT27) P06/(INT26) P05/(INT25) P04/(INT24) P03/(INT23) P02/(INT22) P01/(INT21) MOD1 P00/(INT20) MOD0 P37/BZ/(RCO) P36/INT2 P35/INT1 P40/AN0 P34/TO/INT0 P41/AN1 P33/EC/SCO P42/AN2 P32/SI P43/AN3 P31/SO P30/SCK (DIP-48P-M01) *: The description in the parentheses is available only in the MB89120A series.

  • Page 38: Figure 1.5-3 Mqp-48C-P01 Pin Assignment

    1.5 Pin Assignment MQP-48C-P01 Pin Assignment Figure 1.5-3 MQP-48C-P01 Pin Assignment (Top view) P36/INT2 P37/BZ MOD0 P00/ (INT20) MOD1 P01/ (INT21) P02/ (INT22) P03/ (INT23) P04/ (INT24) P05/ (INT25) P06/ (INT26) P07/ (INT27) *: Pin assignment on package top (MB89PV130A only) Pin no.

  • Page 39: Package Dimensions

    Details of "B" part LEAD No. 0.80(.0315)TYP 0.30 0.10 0.15 0.05 ± ± 0.16(.006) M (.012 .004) (.006 .002) ± ± 0 to10 "B" 0.80 0.30 ± (.031 .012) ± 0.10(.004) c 1994 FUJITSU LIMITED F48023S-1C-1 Dimensions in mm (inches)

  • Page 40: Figure 1.6-2 Dip-48P-M01 Package Dimensions

    Sealing method (DIP-48P-M01) +0.20 43.69 –0.30 +.008 1.720 –.012 INDEX-1 13.80±0.25 (.543±.010) INDEX-2 0.51(.020)MIN .25(.207) 0.25±0.05 .00(.118) (.010±.002) +0.50 1.00 0.45±0.10 15.24(.600) –0 +.020 (.018±.004) 15MAX .039 –0 1.778±0.18 (.070±.007) 1.778(.070) 40.894(1.610)REF Dimensions in mm (inches) 1994 FUJITSU LIMITED D48002S-3C-3...

  • Page 41: Figure 1.6-3 Mqp-48C-P01 Package Dimensions

    PIN No.1 INDEX (.583±.014) (.0315±.0087) 1.02±0.13 (.040±.005) +0.13 10.92 8.71(.343) 7.14(.281) –0.0 +.005 .430 –0 PAD No.1 INDEX 0.30(.012)TYP +0.45 1.10 0.40±0.08 0.60(.024)TYP –0.25 4.50(.177)TYP +.018 (.016±.003) .043 –.010 8.50(.335)MAX 0.15±0.05 (.006±.002) c 1994 FUJITSU LIMITED F48001SC-4-2 Dimensions in mm (inches)

  • Page 42: Pin Functions

    1.7 Pin Functions Pin Functions Tables 1.7-1 and 1.7-2 list the MB89120/120A series I/O pins and their functions. The letter in the "I/O circuit type" column of Tables 1.7-1 and 1.7-2 refer to the letter in the "Type" column of Table 1.8-1. Pin Functions Table 1.7-1 Pin Description Pin no.

  • Page 43: Table 1.7-2 Pin Description For External Eprom Pins (Mb89Pv130A Only)

    CHAPTER 1 OVERVIEW Table 1.7-1 Pin Description (Continued) Pin no. Pin name circuit Function QFP/MQFP* SHDIP type General-purpose I/O port This pin also serves as the external clock input P33/EC/SCO pin for the 8/16-bit timer/counter. The pin is a hysteresis input. The system clock output is optional.
  • Page 44 1.7 Pin Functions Table 1.7-2 Pin Description for External EPROM Pins (MB89PV130A only) (Continued) Pin no. Pin name Function MQFP Address output pins Data input pins Power supply (GND) pin 65 to 69 O4 to O8 Data input pins ROM chip enable pin Outputs "H"...

  • Page 45: I/O Circuit Types

    CHAPTER 1 OVERVIEW I/O Circuit Types Table 1.8-1 lists I/O circuit types of the MB89120/120A series. The letters in the Type column in Table 1.8-1 correspond to those in the I/O circuit type column in Table 1.8-1. I/O Circuit Types Table 1.8-1 I/O Circuit Type Type Circuit...
  • Page 46 1.8 I/O Circuit Types Table 1.8-1 I/O Circuit Type (Continued) Type Circuit Remarks For low-speed operation N-ch P-ch (at subclock oscillation) • Circuit of the MB89121/MB89122A/MB89123A/ MB89125A • Oscillation feedback resistor: Approximately 4.5 N-ch MΩ (at 5 V) Subclock control signal Subclock control signalFor low-speed operation N-ch P-ch (at subclock oscillation)
  • Page 47 CHAPTER 1 OVERVIEW Table 1.8-1 I/O Circuit Type (Continued) Type Circuit Remarks P-ch • CMOS output • Hysteresis input P-ch • Pull-up resistor optional Approximately 50 kΩ/5.0 V N-ch P-ch CMOS output N-ch P-ch • N-ch open-drain output • Pull-up resistor optional Approximately 50 kΩ/5.0 V •...

  • Page 48: Chapter 2 Handling Devices

    CHAPTER 2 HANDLING DEVICES This chapter describes points to note when using the general-purpose single-chip microcontroller. 2.1 Notes on Handling Devices...

  • Page 49: Notes On Handling Devices

    CHAPTER 2 HANDLING DEVICES Notes on Handling Devices This section lists points to note regarding the power supply voltage, pins, and other device handling aspects. Notes on Handling Devices Take great care not to exceed the maximum rated voltage (preventing latchup). or lower than V is applied to Latchup may occur on CMOS ICs if voltage higher than V...
  • Page 50 2.1 Notes on Handling Devices take effect.
  • Page 51 CHAPTER 2 HANDLING DEVICES...

  • Page 52: Chapter 3 Cpu

    CHAPTER 3 This chapter describes the functions and operation of the CPU. 3.1 Memory Space 3.2 Dedicated Registers 3.3 General-purpose Registers 3.4 Interrupts 3.5 Resets 3.6 Clocks 3.7 Standby Modes (Low-power Consumption) 3.8 Memory Access Modes...

  • Page 53: Memory Space

    CHAPTER 3 CPU Memory Space The microcontrollers of the MB89120/120A series offer a memory space of 64 Kbytes. The memory space consists of the I/O area, RAM area, ROM area, and external area. The memory space contains areas used for special purposes such as the general- purpose registers and vector table.

  • Page 54: Figure 3.1-1 Memory Map

    3.1 Memory Space Memory Map Figure 3.1-1 Memory Map MB89121 MB89123A MB89P133A MB89125A MB89P131 MB89P135A MB89PV130A 0000 0000 0000 0000 0000 0080 0080 0080 0080 0080 Access prohibited 0100 0100 0100 0100 0100 Registers Registers Registers 0140 Registers Registers 0180 0180 0200 0200...

  • Page 55: Special Areas

    CHAPTER 3 CPU 3.1.1 Special Areas In addition to the I/O area, the special purpose areas in the memory space include the general-purpose register area and the vector table area. General-purpose Register Area (Addresses: 0100 to 01FF • Provides auxiliary registers for 8-bit arithmetic operation and transfer instructions. •...
  • Page 56 3.1 Memory Space Table 3.1-2 Vector Table (Continued) Vector table address Vector call instruction Upper Lower CALLV #3 FFC6 FFC7 CALLV #4 FFC8 FFC9 CALLV #5 FFCA FFCB CALLV #6 FFCC FFCD CALLV #7 FFCE FFCF Vector table address Interrupts Upper Lower IRQB...

  • Page 57: Storing 16-Bit Data In Memory

    CHAPTER 3 CPU 3.1.2 Storing 16-bit Data in Memory For 16-bit data and the stack, store the upper data in the lower memory address value. Storing 16-bit Data in RAM When writing 16-bit data to memory, store the upper byte at the lower address and the lower byte at the next address.
  • Page 58 3.1 Memory Space Storing 16-bit Data on Stack The same byte order applies when saving 16-bit register data on the stack during an interrupt or similar. The upper byte is stored in the lower address.

  • Page 59: Dedicated Registers

    CHAPTER 3 CPU Dedicated Registers The dedicated registers in the CPU consist of the program counter (PC), two arithmetic operation registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS). All registers are 16 bits. Dedicated Register Configuration The dedicated registers in the CPU consist of seven 16-bit registers.
  • Page 60 3.2 Dedicated Registers of the accumulator after a reset is indeterminate. Temporary accumulator (T) The temporary accumulator is an auxiliary 16-bit arithmetic operation register used to perform arithmetic operations with the data in the accumulator (A). The content of the temporary accumulator is treated as word data (16-bit) for word-length arithmetic operations with the accumulator and as byte data (8-bit) for byte-length arithmetic operations.

  • Page 61: Condition Code Register (Ccr)

    CHAPTER 3 CPU 3.2.1 Condition Code Register (CCR) The condition code register (CCR) located in the lower 8 bits of the program status (PS) consists of the C, V, Z, N, and H bits indicating the results of arithmetic operations and the contents of transfer data, and the I, IL1, and IL0 bits for control whether or not the CPU accepts interrupt requests.

  • Page 62: Figure 3.2-3 Change Of Carry Flag By Shift Instruction

    3.2 Dedicated Registers Cleared to "0" otherwise. Set to the shift-out value in case of a shift instruction. Figure 3.2-3 shows the change of the carry flag by a shift instruction. Figure 3.2-3 Change of Carry Flag by Shift Instruction •...
  • Page 63 CHAPTER 3 CPU Tip: The interrupt level bits (IL1, IL0) are normally "11" when the CPU is not processing an interrupt (during main program execution). Reference: See Section 3.4, "Interrupts" for details on interrupts.

  • Page 64: Register Bank Pointer (Rp)

    3.2 Dedicated Registers 3.2.2 Register Bank Pointer (RP) The register bank pointer (RP) located in the upper 8 bits of the program status (PS) indicates the address of the general-purpose register bank currently in use. The RP is converted to form the actual address in general-purpose register addressing. Structure of Register Bank Pointer (RP) Figure 3.2-4 shows the structure of the register bank pointer.

  • Page 65: General-Purpose Registers

    CHAPTER 3 CPU General-Purpose Registers The general-purpose registers are a memory block made up of banks, with 8 × 8-bit registers per bank. The register bank pointer (RP) is used to specify the register bank. In functional terms, a total of 32 banks are available. If the internal RAM size is insufficient for all banks, all of the banks may not be always available.
  • Page 66 3.3 General-Purpose Registers Features of General-purpose Registers General-purpose registers have the following features: • RAM can be accessed at high-speed using short instructions (general-purpose register addressing). • Registers are grouped in blocks in the form of register banks. This simplifies the process of protecting register contents and dividing registers by function.

  • Page 67: Interrupts

    CHAPTER 3 CPU Interrupts The MB89120/120A series has 8 interrupt request inputs corresponding to peripheral functions. An interrupt level can be set independently. If an interrupt request output is enabled in the peripheral function, an interrupt request from a peripheral function is compared with the interrupt level in the interrupt controller.
  • Page 68 3.4 Interrupts *: Avaliable for the MB89120A series only.

  • Page 69: Interrupt Level Setting Registers (Ilr1, Ilr2, Ilr3)

    CHAPTER 3 CPU 3.4.1 Interrupt Level Setting Registers (ILR1, ILR2, ILR3) The interrupt level setting registers (ILR1, ILR2, ILR3) together contain 12 blocks of 2- bit data, with each data corresponding to an interrupt request from a peripheral function. The interrupt level for each interrupt is set in that interrupt’s corresponding 2-bit data (interrupt level setting bits).
  • Page 70 3.4 Interrupts Check: As the IRL1, ILR2, and ILR3 registers are write-only, the bit manipulation instructions(SETB, CLRB) cannot be used.

  • Page 71: Interrupt Processing

    CHAPTER 3 CPU 3.4.2 Interrupt Processing The interrupt controller transmits the interrupt level to the CPU when an interrupt request is generated by a peripheral function. If the CPU is able to receive the interrupt, the CPU temporarily halts the currently executing program and executes the interrupt processing routine.

  • Page 72: Figure 3.4-2 Interrupt Processing

    3.4 Interrupts Figure 3.4-2 Interrupt Processing Condition code register (CCR) Register file Comparator IPLA Check MC-8L·CPU Wake-up from stop mode START Wake-up from sleep mode Wake-up from watch mode Initialize peripheral · · · Enable FF Is an interrupt request present at the Request FF peripheral? Interrupt...
  • Page 73 CHAPTER 3 CPU The interrupt request flag bit (request FF) for a peripheral function is set to "1" when the peripheral function generates an interrupt source. If the interrupt request enable bit for the peripheral function is set to "enable" (enable FF = "1"), the peripheral function outputs the interrupt request to the interrupt controller.

  • Page 74: Multiple Interrupts

    3.4 Interrupts 3.4.3 Multiple Interrupts Multiple interrupts can be performed by setting different interrupt levels to the interrupt level setting register (ILR1 to ILR3) for two or more interrupt requests from peripheral functions. Multiple Interrupts If the interrupt request having the higher interrupt levels occurs during the interrupt processing routines, the CPU halts the current interrupt process and switches to accept the interrupt with the higher priority.
  • Page 75 CHAPTER 3 CPU saved on the stack and resumes execution of the interrupted program. Restoring the program status (PS) returns the condition code register (CCR) to the value prior to the interrupt.

  • Page 76: Interrupt Processing Time

    3.4 Interrupts 3.4.4 Interrupt Processing Time The total time from the generation of an interrupt request until control passes to the interrupt processing routine is the sum of the time required to complete execution of the current instruction and the interrupt handling time (the time required to prepare for interrupt processing).
  • Page 77 CHAPTER 3 CPU function). See Section 3.6, "Clocks" for details.

  • Page 78: Stack Operation During Interrupt Processing

    3.4 Interrupts 3.4.5 Stack Operation during Interrupt Processing This section describes the saving of the register contents to the stack and restore operation during interrupt processing. Stack Operation at Start of Interrupt Processing The CPU automatically saves the current contents of the program counter (PC) and program status (PS) to the stack when an interrupt is accepted.

  • Page 79: Stack Area For Interrupt Processing

    CHAPTER 3 CPU 3.4.6 Stack Area for Interrupt Processing Interrupt processing execution uses the stack area in RAM. The contents of the stack pointer (SP) specifies the top address of the stack area. Stack Area for Interrupt Processing The subroutine call instruction (CALL) and vector call instruction (CALLV) use the stack area to save and restore the program counter (PC).

  • Page 80: Resets

    3.5 Resets Resets The MB89120/120A series supports the following four types of reset source: • External reset • Software reset • Watchdog reset • Power-on reset (optional) Generation of the main clock oscillation stabilization delay time depends on the operation mode or option setting. Reset Source Table 3.5-1 Reset Source Reset source...

  • Page 81: Table 3.5-2 Reset Source And Oscillation Stabilization Delay Time

    CHAPTER 3 CPU Upon completion of reset operation, the CPU restarts normal operation in main clock mode, regardless of the operation mode (clock or standby mode) prior to the occurrence of the reset or the reset source. If a reset occurs when main clock oscillation stops or during the main clock oscillation stabilization delay time, therefore, the CPU enters the reset state in which it waits until oscillation of the main clock becomes stable.

  • Page 82: External Reset Pin

    3.5 Resets 3.5.1 External Reset Pin Inputting an "L" level to the external reset pin generates a reset. If products are set to with the reset output (optional), the pin outputs an "L" level depending on internal reset sources. Block Diagram of External Reset Pin The external reset pin (RST) on products with the reset output is a hysteresis input type and N- ch open-drain output type with a pull-up resistor.

  • Page 83: Reset Operation

    CHAPTER 3 CPU 3.5.2 Reset Operation When the CPU wakes up from a reset, the CPU selects the read address of the mode data and reset vector according to the mode pin settings, then performs a mode fetch. The mode fetch is performed after the oscillation stabilization delay time has passed when power is turned on to a product with power-on reset option, or on wake-up from subclock or stop mode by a reset.
  • Page 84 3.5 Resets Mode Pins The MB89120/120A series works only in the single-chip mode. Be sure to set mode pins (MOD1, MOD0) to "Vss, Vss". The internal ROM is specified as the destination for mode data and reset vector read out. Do not change the mode pin settings, even after the reset has completed.

  • Page 85: Pin States During Reset

    CHAPTER 3 CPU 3.5.3 Pin States During Reset A reset initializes the pin state. Pin States during Reset When a reset source is generated, all I/O pins (peripheral pins), with some exceptions, go to the high-impedance state and the mode data is read from internal ROM (pins with a pull-up resistor (optional) go to the "H"...

  • Page 86: Clocks

    3.6 Clocks Clocks The clock generator incorporates a pair of oscillators. The oscillators can be connected each to an external resonator to generate high-speed main clock and low- speed subclock signals (for source oscillation). They can also input externally generated clock signals. Dual-clock signals are controlled in speed and supply for each clock mode and standby mode by the clock controller.

  • Page 87: Figure 3.6-1 Clock Supply Map

    CHAPTER 3 CPU Figure 3.6-1 shows the clock supply map. Figure 3.6-1 Clock Supply Map Peripheral functions Main clock *1, *3 Timebase timer Divide-by-two Watchdog timer oscillator Clock controller 8/16-bit timer/counter Clock mode Stop mode Divide-by-four Gear function Divide-by-eight 8-bit serial I/O Divide-by-16 Divide-by-64 Buzzer output...

  • Page 88: Clock Generator

    3.6 Clocks 3.6.1 Clock Generator Enable and stop of the main clock and subclock oscillation is controlled by watch mode and stop mode. Clock Generator Crystal or ceramic resonator Connect as shown in Figure 3.6-2. Figure 3.6-2 Connection Example for Crystal or Ceramic Resonator Dual-clock option Single-clock option Main clock...

  • Page 89: Figure 3.6-3 Connection Example For External Clock

    CHAPTER 3 CPU External Clock Connect an external clock to the X0 pin and leave the X1 pin open, as shown in Figure 3.6-3. Since the external clock input cannot be used for the subclock, be sure to connect a resonator. Figure 3.6-3 Connection Example for External Clock Dual-clock option Single-clock option...

  • Page 90: Clock Controller

    3.6 Clocks 3.6.2 Clock Controller The clock controller contains the following seven blocks: • Main clock oscillator • Subclock oscillator • System clock selector • Clock controller • Oscillation stabilization delay time selector • System clock control register (SYCC) • Standby control register (STBC) Blcok Diagram of Clock Controller Figure 3.6-4 shows the block diagram of the clock controller.
  • Page 91 CHAPTER 3 CPU Subclock oscillator This oscillator is the oscillation circuit for the subclock. It always oscillates except in sub-stop mode. The oscillator does not operate with the single-clock option selected. System clock selector This selector selects one of the four different clock signals obtained by dividing the oscillation frequency of the main clock or the subclock signal and supplies it to the clock controller.

  • Page 92: System Clock Control Register (Sycc)

    3.6 Clocks 3.6.3 System Clock Control Register (SYCC) The system clock control register (SYCC) is used to switch between the main clock and subclock, select the main clock speed, and select the oscillation stabilization delay time. Structure of System Clock Control Register (SYCC) Figure 3.6-5 System Clock Control Register (SYCC) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address...

  • Page 93: Table 3.6-1 System Clock Control Register (Sycc) Bits

    CHAPTER 3 CPU Table 3.6-1 System Clock Control Register (SYCC) Bits Function • This bit checks the current clock mode (operating clock). • When the bit is "0", the CPU is operating in subclock mode (with SCM: the main clock off or in oscillation stabilization delay state). System Bit 7 •...
  • Page 94 3.6 Clocks In subclock mode (SCS = 0), the instruction cycle is 2/FCL = approx. 61.0 µs at a subclock oscillation (F ) of 32.768 kHz.

  • Page 95: Clock Modes

    CHAPTER 3 CPU 3.6.4 Clock Modes There are two clock modes available: main clock and subclock modes. In main clock mode, the main clock serves as the major operating clock. The main clock speed can be switched by selecting one of the four different clock signals produced by dividing the oscillation frequency (using the clock gear function).
  • Page 96 3.6 Clocks Table 3.6-2 Operating States in Each Clock Mode (Continued) Clock generation Operating clock for each module Standby mode Main clock wake-up Clock speed SYCC Standby Time- Watch source Main Sub- mode register (CS1, mode base ripher- pre- (other clock clock CS0)
  • Page 97 CHAPTER 3 CPU Switching from main clock mode to subclock mode Writing "0" to the system clock select bit (SCS) in the system clock control register (SYCC) switches the CPU from main clock mode to subclock mode. The current operating clock can be checked by reading the system clock monitor bit (SCM) in the system clock control register (SYCC).

  • Page 98: Oscillation Stabilization Delay Time

    3.6 Clocks 3.6.5 Oscillation Stabilization Delay Time As the main clock remains stopped before the power is turned on, during main stop mode or subclock mode, a main clock oscillation stabilization delay time is required to enter the main-RUN operation mode. Similarly, in subclock mode, a subclock oscillation stabilization delay time is required since the subclock oscillation is stopped.

  • Page 99: Table 3.6-3 Main Clock Mode Operation Start Conditions And Oscillation Stabilization Delay Time

    CHAPTER 3 CPU Oscillation stabilization delay time after a reset The oscillation stabilization delay time (the WT1 and WT0 initial values) taken after a reset is selected by option settings. The product with the power-on reset function requires the oscillation stabilization delay time after resets in subclock mode, a power-on reset, or an external reset to cancel the stop mode.

  • Page 100: Standby Modes (Low-Power Consumption)

    3.7 Standby Modes (Low-power Consumption) Standby Modes (Low-power Consumption) The standby modes consist of sleep mode, stop mode, and watch mode. Standby modes are changed to sleep mode or stop mode by setting the standby control register (STBC). The main clock mode enables transition to sleep or stop mode. The subclock mode enables transition to sleep, stop or watch mode.
  • Page 101 CHAPTER 3 CPU buzzer outputs and the peripheral control clock output can work with the subclock if the subclock is oscillating. For details, see Chapter 9 "Buzzer Output," Chapter 14 "Peripheral Contorl Clock Output," and "Clock Supply Map" in Section 3.6 "Clocks."...

  • Page 102: Standby Mode Operating States

    3.7 Standby Modes (Low-power Consumption) 3.7.1 Standby Mode Operating States This section describes the operating states of the CPU and peripheral functions in each standby mode. Standby Mode Operating States Table 3.7-1 Operating States of the CPU and Peripheral Functions in Standby Mode Operating mode Main clock mode Subclock mode...
  • Page 103 CHAPTER 3 CPU While the watch prescaler increments, no watch interrupt is generated. These functions can operate if the watch prescaler output or subclock frequency- divided output has been selected for the operating clock. Pin states in standby mode By using the pin state specification bit (SPL) in the standby control register (STBC), most I/O pins can hold the state immediately prior to transition to the stop or watch mode or can be placed in a high-impedance state regardless of the current clock mode.

  • Page 104: Sleep Mode

    3.7 Standby Modes (Low-power Consumption) 3.7.2 Sleep Mode This section describes the operations of sleep mode. Operation of Sleep Mode Changing to sleep mode Sleep mode stops the CPU operating clock. The CPU stops while maintaining all register contents and RAM contents, at their values immediately prior to entering sleep mode. However, peripheral functions except the watchdog timer continue to operate.

  • Page 105: Stop Mode

    CHAPTER 3 CPU 3.7.3 Stop Mode This section describes the operations of stop mode. Operation of Stop Mode Changing to stop mode Stop mode stops the source oscillation. Most CPU and peripheral functions stop while maintaining all register and RAM contents at their values immediately before changing to stop mode.
  • Page 106 3.7 Standby Modes (Low-power Consumption) Some peripheral functions restart from mid-operation when the CPU wakes up from stop mode by an external interrupt. Accordingly, the first interval time for the interval timer function, for example, becomes indeterminate. Therefore, initialize all peripheral functions after wake-up from stop mode.

  • Page 107: Watch Mode

    CHAPTER 3 CPU 3.7.4 Watch Mode This section describes operations in watch mode. Operations in Watch Mode Changing to watch mode Watch mode stops the CPU and the operating clock for major peripheral circuits. The CPU can enter this mode only when it is in subclock mode (with the main clock stopping oscillation). Watch mode maintains the contents of registers and RAM, which they have immediately before the CPU enters the mode, and stops all the functions except the watch prescaler (watch interrupt), external interrupt circuit, and some subclock-based functions.

  • Page 108: Standby Control Register (Stbc)

    3.7 Standby Modes (Low-power Consumption) 3.7.5 Standby Control Register (STBC) The standby control register (STBC) controls the changing to sleep mode, stop mode, or watch mode, sets the pin states in stop or watch mode, and initiates software resets. Standby Control Register (STBC) Figure 3.7-1 Standby Control Register (STBC) Address Bit 7...

  • Page 109: Table 3.7-2 Standby Control Register (Stbc) Bits

    CHAPTER 3 CPU Table 3.7-2 Standby Control Register (STBC) Bits Function • Sets the CPU changing to stop mode. STP: • Writing "1" to this bit causes the CPU change to stop mode. Bit 7 Stop bit • Writing "0" to this bit has no effect on operation. •...

  • Page 110: State Transition Diagram 1 (Product With Power-On Reset Function In Dual-Clock Configuration)

    3.7 Standby Modes (Low-power Consumption) 3.7.6 State Transition Diagram 1 (Product with Power-on Reset Function in Dual-clock Configuration) This section provides the state transition diagram for the product with the power-on reset function in the dual-clock configuration. State Transition Diagram 1 (Product with Power-on Reset Function in Dual-clock Configuration) Figure 3.7-2 State Transition Diagram 1 (Product with Power-on Reset Function in Dual-clock Configuration) Power on...

  • Page 111: Table 3.7-3 Switching To And From Clock Mode (Product With Power-On Reset Function In Dual-Clock Configuration)

    CHAPTER 3 CPU Switching to and from clock mode (not in standby mode) Table 3.7-3 Switching to and from Clock Mode (Product with Power-on Reset Function in Dual-clock Configuration) State transition Transition conditions End of main clock oscillation stabilization delay time (Timebase timer Transition to normal (main- output) RUN) state in main clock...
  • Page 112 3.7 Standby Modes (Low-power Consumption) Table 3.7-4 Switching to and from Standby Mode (Product with Power-on Reset Function in Dual-clock Configuration) Transition conditions State transition main clock mode Subclock mode External interrupt <5> External interrupt End of main clock oscillation <6>...

  • Page 113: State Transition Diagram 2 (Product Without Power-On Reset Function In Dual-Clock Configuration)

    CHAPTER 3 CPU 3.7.7 State Transition Diagram 2 (Product without Power-on Reset Function in Dual-clock Configuration) This section provides the state transition diagram for the product without the power-on reset function in the dual-clock configuration. State Transition Diagram 2 (Product without Power-on Reset Function in Dual-clock Configuration) Figure 3.7-3 State Transition Diagram 2 (Product without Power-on Reset Function in Dual-clock Configuration) Power on...
  • Page 114 3.7 Standby Modes (Low-power Consumption) Switching to and from clock mode (not in standby mode) Table 3.7-5 Switching to and from Clock Mode (Product without Power-on Reset Function in Dual-clock Configuration) State transition Transition conditions External reset input is required until oscillation of the main clock Transition to normal (main- becomes stable.
  • Page 115 CHAPTER 3 CPU Switching to and from standby mode Table 3.7-6 Switching to and from Standby Mode (Product without Power-on Reset Function in Dual- clock Configuration) Transition conditions State transition main clock mode Subclock mode Transition to sleep STBC : SLP= "1" <1>...

  • Page 116: State Transition Diagram 3 (Products In Single-Clock Configuration)

    3.7 Standby Modes (Low-power Consumption) 3.7.8 State Transition Diagram 3 (Products in Single-clock Configuration) This section provides the state transition diagram for the product with the power-on reset function and that for the product without the power-on reset function, both in the single-clock configuration.

  • Page 117: Table 3.7-7 Switching To Main Clock Mode Run State And Reset (Product In Single-Clock Configuration)

    CHAPTER 3 CPU Switching to normal (RUN) state and reset Table 3.7-7 Switching to Main clock Mode Run State and Reset (Product in Single-clock Configuration) Transition conditions State transition Product with power-on reset function Product without power-on reset (Figure 3.7-4) function (Figure 3.7-5) End of main clock oscillation External reset input is required until...

  • Page 118: Pin States In Standby Modes

    3.7 Standby Modes (Low-power Consumption) 3.7.9 Pin States in Standby Modes Table 3.7-9 lists the pin states in standby modes. Pin States in Standby Modes Table 3.7-9 Pin States in Standby Modes Stop mode Stop mode Watch Watch Sleep mode (SPL="0") (SPL="1") mode...
  • Page 119 CHAPTER 3 CPU The pins enclosed in ( ) are valid only in the MB89120A series. Hi-z: High impedance SPL: Pin state specification bit in the standby control register (STBC) Hold: The pin set as output, holds its state (level) immediately before changing to each mode.

  • Page 120: 3.7.10 Notes On Using Standby Modes

    3.7 Standby Modes (Low-power Consumption) 3.7.10 Notes on Using Standby Modes The CPU does not change to a standby mode if an interrupt request occurs from a peripheral function when a standby mode is set in the standby control register (STBC). Also, if an interrupt is used to wake up from a standby mode to the normal operating state, the operation after wake-up differs depending on whether or not the interrupt request is accepted.

  • Page 121: Table 3.7-10 Low-Power Consumption Mode Settings In Standby Control Register (Stbc)

    CHAPTER 3 CPU Writing to the watch bit (TMD) is ignored during operation in main clock mode. Table 3.7-10 Low-power Consumption Mode Settings in Standby Control Register (STBC) STBC register Mode STP (bit 7) SLP (bit 6) TMD (bit 3) Normal Watch Sleep...

  • Page 122: Memory Access Modes

    3.8 Memory Access Modes Memory Access Modes The memory access mode supported by the MB89120/120AMB89120A series is only single-chip mode. Single-chip Mode In single-chip mode, the device uses internal RAM and ROM only. Therefore, the CPU can only access to internal I/O, RAM and ROM areas. Mode Pins (MOD0, MOD1) Mode pins (MOD1 and MOD0) must be set to "V ".

  • Page 123: Figure 3.8-2 Memory Access Selection Operation

    CHAPTER 3 CPU Memory Access Mode Selection Operation Other setting than the single-chip mode is not enabled. Table 3.8-2 lists the mode pins and mode data. Table 3.8-2 Mode Pins and Mode Data Memory access mode Mode pins (MOD0, MOD1) Mode data Single-chip mode Other modes...

  • Page 124: Chapter 4 I/O Ports

    CHAPTER 4 I/O PORTS This chapter describes the functions and operation of the I/O ports. 4.1 Overview of I/O Ports 4.2 Port 0 4.3 Port 1 4.4 Port 2 4.5 Port 3 4.6 Port 4 4.7 Program Example for I/O Ports...

  • Page 125: Overview Of I/O Ports

    CHAPTER 4 I/O PORTS Overview of I/O Ports The I/O ports consist of five ports (36 pins) including output-only ports and general- purpose I/O ports (parallel I/O ports). The ports also serve as resource pins (I/O pins of peripheral functions). I/O Port Functions The functions of the I/O ports are to output data from the CPU to the I/O pins and to fetch signals input to the I/O pins into the CPU.

  • Page 126: Table 4.1-2 Port Registers

    4.1 Overview of I/O Ports Table 4.1-1 Port Function (Continued) Port Input Output Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 name type type Output-only N-ch — — — — port P40 to Port 4 —...

  • Page 127: Port 0

    CHAPTER 4 I/O PORTS Port 0 Port 0 is a general-purpose I/O port. The port 2 also serves as the external interrupt 2 input pins in the MB89120A series. This section principally describes the port functions when operating as a general- purpose I/O port.

  • Page 128: Table 4.2-1 Port 0 Pins

    4.2 Port 0 Table 4.2-1 lists the port 0 pins. Table 4.2-1 Port 0 Pins I/O type Circuit Port Pin name Function Shared peripheral type Input Output INT20*1 Externel interrupt 2 P00/INT20* P00 General-purpose I/O input INT21*1 Externel interrupt 2 P00/INT21* P01 General-purpose I/O input...

  • Page 129: Figure 4.2-1 Block Diagram Of Port 0 Pin

    CHAPTER 4 I/O PORTS Block Diagram of Port 0 Figure 4.2-1 Block Diagram of Port 0 Pin Pull-up resistor To externel interrupt (optional) (MB89120A only) Approx. 50 k /5.0 V PDR (Port data register) Stop or watch mode (SPL=1) PDR read P-ch PDR read (for bit manipulation instructions) Output latch...

  • Page 130: Port 0 Registers (Pdr0, Ddr0)

    4.2 Port 0 4.2.1 Port 0 Registers (PDR0, DDR0) This section describes the port 0 registers. Port 0 Register Functions Port data register (PDR0) The PDR0 register holds the states of pins. From the bit corresponding to a pin set as an output port pin, therefore, the same value ("0"...
  • Page 131 CHAPTER 4 I/O PORTS Table 4.2-3 Port 0 Register Functions (Continued) Read/ Register Data Read Write Address Initial value Write Sets the output buffer to "OFF" Reading and sets the pin as an input Port 0 data is not pin. direction permitted 0001...

  • Page 132: Operation Of Port 0

    4.2 Port 0 4.2.2 Operation of Port 0 This section describes the operation of the port 0. Operation of Port 0 Operation as an output port • Setting the corresponding DDR0 register bit to "1" sets a pin as an output port. •...

  • Page 133: Table 4.2-4 Port 0 Pin States

    CHAPTER 4 I/O PORTS Table 4.2-4 lists the port 0 pin states. Table 4.2-4 Port 0 Pin States Normal operation Main-sleep mode Main-stop mode(SPL = 1) Main-stop mode (SPL = 0) Pin name Sub-stop mode (SPL = 1) Reset Sub-sleep mode Watch mode (SPL = 1) Sub-stop mode(SPL = 0) Watch mode (SPL = 0)

  • Page 134: Port 1

    4.3 Port 1 Port 1 Port 1 is a general-purpose I/O port. This section describes the port structure and pins, the pin block diagram, and the port registers for port 1. Structure of Port 1 Port 1 consists of the following three components: •...

  • Page 135: Figure 4.3-1 Block Diagram Of Port 1 Pin

    CHAPTER 4 I/O PORTS Block Diagram of Port 1 Figure 4.3-1 Block Diagram of Port 1 Pin Pull-up resistor (optional) Approx. 50 k /5.0 V PDR (Port data register) Stop or watch mode (SPL=1) PDR read P-ch PDR read (for bit manipulation instructions) Output latch P-ch PDR write...

  • Page 136: Port 1 Registers (Pdr1, Ddr1)

    4.3 Port 1 4.3.1 Port 1 Registers (PDR1, DDR1) This section describes the port 1 registers. Port 1 Register Functions Port 1 data register (PDR1) The PDR1 register holds the states of pins. From the bit corresponding to a pin set as an output port pin, therefore, the same value ("0"...
  • Page 137 CHAPTER 4 I/O PORTS R/W: Readable and writable Write-only Indeterminate...

  • Page 138: Operation Of Port 1

    4.3 Port 1 4.3.2 Operation of Port 1 This section describes the operations of port 1. Operation of Port 1 Operation as an output port • Setting the DDR1 register bit corresponding to a port 1 pin to "1" sets the pin as an output port pin.

  • Page 139: Table 4.3-4 Port 1 Pin States

    CHAPTER 4 I/O PORTS Table 4.3-4 lists the port 1 pin states. Table 4.3-4 Port 1 Pin States Normal operation Main-stop mode (SPL = 1) Main-sleep mode Sub-stop mode (SPL = 1) Main-stop mode (SPL = 0) Watch mode (SPL = 1) Pin name Reset Sub-sleep mode...

  • Page 140: Port 2

    4.4 Port 2 Port 2 Port 2 is an output-only port. The section describes the port structure and pins, the pin block diagram, and the port registers for port 2. Structure of Port 2 Port 2 consists of the following two components: •...

  • Page 141: Figure 4.4-1 Block Diagram Of Port 2 Pin

    CHAPTER 4 I/O PORTS Block Diagram of Port 2 Figure 4.4-1 Block Diagram of Port 2 Pin PDR (Port data register) PDR read Output latch P-ch PDR write N-ch Stop or watch mode (SPL=1) SPL: Pin state specification bit in the standby control register (STBC) Port 2 Register The port 2 register is of PDR2.

  • Page 142: Port 2 Register (Pdr2)

    4.4 Port 2 4.4.1 Port 2 Register (PDR2) This section describes the functions of the port 2 register. Port 2 Register Functions Port 2 data register (PDR2) The PDR2 register indicates the state of output latch. Therefore, the pin state cannot be read. Table 4.4-3 lists the functions of the port 2 register.

  • Page 143: Operation Of Port 2

    CHAPTER 4 I/O PORTS 4.4.2 Operation of Port 2 This section describes the operations of port 2. Operation of Port 2 Operation as an output-only port • Writing data to the PDR2 register stores the data in the output latch and outputs the data to the pin via the output buffer.

  • Page 144: Port 3

    4.5 Port 3 Port 3 Port 3 is a general-purpose I/O port that also serves as peripheral I/O. Each pin can be switched between peripheral and port operation in bit units. This section principally describes the port functions when operating as a general-purpose I/O port. The section describes the port structure and pins, the pin block diagram, and the port registers for port 3.

  • Page 145: Figure 4.5-1 Block Diagram Of Port 3 Pins (P30 To P32, P34 To P36)

    CHAPTER 4 I/O PORTS *1: The system clock output is optional on the MB89121. *2: The remote-control transmission frequency output is available only in the MB89120A series. Reference: See Section 1.7, "I/O Pins and Pin Functions" for a description of the circuit type. Block Diagram of Port 3 Figure 4.5-1 Block Diagram of Port 3 Pins (P30 to P32, P34 to P36) Pull-up resistor...

  • Page 146: Table 4.5-2 Correspondence Between Pins And Registers For Port 3

    4.5 Port 3 Port 3 Registers The port 3 registers consist of PDR3 and DDR3. Each bit in these registers has a one-to-one relationship with a port 3 pin. Table 4.5-2 shows the correspondence between pins and registers for port 3. Table 4.5-2 Correspondence between Pins and Registers for Port 3 Port Correspondence between register bit and pin...

  • Page 147: Port 3 Registers (Pdr3, Ddr3)

    CHAPTER 4 I/O PORTS 4.5.1 Port 3 Registers (PDR3, DDR3) This section describes the port 3 registers. Port 3 Register Functions Port 3 data register (PDR3) The PDR3 register holds the states of pins. From the bit corresponding to a pin set as an output port pin, therefore, the same value ("0"...

  • Page 148: Table 4.5-3 Port 3 Register Function

    4.5 Port 3 Table 4.5-3 lists the functions of the port 3 registers. Table 4.5-3 Port 3 Register Function Read/ Register Data Read Write Address Initial value Write Sets "0" to the output latch. Pin state is the Outputs an "L" level to the pin "L"...

  • Page 149: Operation Of Port 3

    CHAPTER 4 I/O PORTS 4.5.2 Operation of Port 3 This section describes the operations of the port 3. Operation of Port 3 Operation as an output port • Setting the corresponding DDR3 register bit to "1" sets a pin as an output port. •...

  • Page 150: Table 4.5-4 Port 3 Pin State

    4.5 Port 3 Operation in stop mode and watch mode The pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device changes to stop or watch mode. This is achieved by forcibly setting the output buffer to "OFF"...

  • Page 151: Port 4

    CHAPTER 4 I/O PORTS Port 4 Port 4 is an output-only port. The section describes the port structure and pins, the pin block diagram, and the port register for port 4. Structure of Port 4 Port 4 consists of the following two components: •...

  • Page 152: Figure 4.6-1 Block Diagram Of Port 4 Pin

    4.6 Port 4 Block Diagram of Port 4 Figure 4.6-1 Block Diagram of Port 4 Pin PDR (Port data register) P-ch PDR read Output latch P-ch PDR write N-ch Stop or watch mode (SPL=1) SPL: Pin state specification bit in the standby control register (STBC) Port 4 Register The port 4 register is of PDR4.

  • Page 153: Port 4 Register (Pdr4)

    CHAPTER 4 I/O PORTS 4.6.1 Port 4 Register (PDR4) This section describes the port 4 register. Port 4 Register Functions Port 4 data register (PDR4) The PDR4 register holds the output latch state. The pin state cannot therefore be read from this register.

  • Page 154: Operation Of Port 4

    4.6 Port 4 4.6.2 Operation of Port 4 This section describes the operations of the port 4. Operation of Port 4 Operation as an output port • Writing data to the PDR4 register stores the data in the output latch. When the output latch value is "0", the output transistor turns "ON"...

  • Page 155: Program Example For I/O Ports

    CHAPTER 4 I/O PORTS Program Example for I/O Ports This section gives an example program using the I/O ports. Program Example for I/O Ports Processing description • Ports 0 and 1 are used to illuminate all elements of a seven segment LED (eight segments if the decimal point is included).
  • Page 156 4.7 Program Example for I/O Ports DDR0,#11111111B ; Set P00 as an output (#xxxxxxx1B). DDR1,#11111111B ; Set all port 1 pins as outputs (all bits). ENDS ;--------------------------------------------------------------------------------------------------------------------------------------------...
  • Page 157 CHAPTER 4 I/O PORTS...

  • Page 158: Chapter 5 Timebase Timer

    CHAPTER 5 TIMEBASE TIMER This chapter describes the functions and operation of the timebase timer. 5.1 Overview of Timebase Timer 5.2 Structure of Timebase Timer 5.3 Timebase Timer Control Register (TBTC) 5.4 Timebase Timer Interrupt 5.5 Operation of Timebase Timer 5.6 Notes on Using Timebase Timer 5.7 Program Example for Timebase Timer...

  • Page 159: Overview Of Timebase Timer

    CHAPTER 5 TIMEBASE TIMER Overview of Timebase Timer The timebase timer uses a 21-bit free-run counter which counts-up in sync with the internal count clock (divide-by-two main clock source oscillation). The timebase timer provides interval timer functions. Four different interval times can be selected. The timebase timer also provides the timer output for the oscillation stabilization delay time and the operating clock for the watchdog and other timers.
  • Page 160 5.1 Overview of Timebase Timer Table 5.1-2 Clock Supplied by Timebase Timer (Continued) Clock destination Clock cycle Remarks Count-up clock for the watchdog Watchdog timer (approx. 998.6 ms) timer Buzzer output to 2 (approx. 0.12 to 0.98 ms) See Chapter 9, “Buzzer Output.” : Main clock source oscillation Values in parentheses are values at 4.2-MHz main clock oscillation mode.

  • Page 161: Structure Of Timebase Timer

    CHAPTER 5 TIMEBASE TIMER Structure of Timebase Timer The timebase timer consists of the following four blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) Block Diagram of Timebase Timer Figure 5.2-1 Block Diagram of Timebase Timer To watchdog timer To buzzer output...
  • Page 162 5.2 Structure of Timebase Timer Timebase timer control register (TBTC) The TBTC register is used to select the interval time, clear the counter, control interrupts, and check the state of the timebase timer.

  • Page 163: Timebase Timer Control Register (Tbtc)

    CHAPTER 5 TIMEBASE TIMER Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) is used to select the interval timer bit, clear the counter, control interrupts, and check the state of the timebase timer. Timebase Timer Control Register (TBTC) Figure 5.3-1 Timebase Timer Control Register (TBTC) Address Bit 7...
  • Page 164 5.3 Timebase Timer Control Register (TBTC) Table 5.3-1 Timebase Timer Control Register (TBTC) Bits (Continued) Function This bit enables or disables an interrupt request output to the TBIE: Bit 6 CPU. An interrupt request is output when both this bit and Interrupt request enable bit the overflow interrupt request flag bit (TBOF) are "1".

  • Page 165: Timebase Timer Interrupt

    CHAPTER 5 TIMEBASE TIMER Timebase Timer Interrupt The timebase timer can generate an interrupt request when an overflow occurs on the specified bit of the timebase timer counter (for the interval timer function). Interrupts for Interval Timer Function The counter counts up on the internal count clock. When an overflow occurs on the selected interval timer bit, the overflow interrupt request flag bit (TBTC: TBOF) is set to "1".

  • Page 166: Operation Of Timebase Timer

    5.5 Operation of Timebase Timer Operation of Timebase Timer The timebase timer has the interval timer function and the clock supply function for some peripherals. Operation of Interval Timer Function (Timebase Timer) Figure 5.5-1 shows the settings required to operate the interval timer function. Figure 5.5-1 Interval Timer Function Settings Bit 7 Bit 6...

  • Page 167: Figure 5.5-2 Timebase Timer Operation

    CHAPTER 5 TIMEBASE TIMER Figure 5.5-2 Timebase Timer Operation Counter value 1FFFFF Cleared by changing to main-stop mode. oscillation stabilization delay overflow 00000 Counter clear Interval cycle CPU operation starts (TBTC: TBR = “0”) (TBTC: TBC1, TBC0 = “11H”) Power-on reset Cleared by the interrupt (optional) processing routine.

  • Page 168: Notes On Using Timebase Timer

    5.6 Notes on Using Timebase Timer Notes on Using Timebase Timer This section lists points to note when using the timebase timer. Notes on Using Timebase Timer Notes on setting bits by program The system cannot recover from interrupt processing if the overflow interrupt request flag bit (TBTC: TBOF) is "1"...

  • Page 169: Figure 5.6-1 Effect On Buzzer Output Of Clearing Timebase Timer

    CHAPTER 5 TIMEBASE TIMER Figure 5.6-1 shows the effect on the buzzer output of clearing the timebase timer. Figure 5.6-1 Effect on Buzzer Output of Clearing Timebase Timer Counter value XXX3FF XXX200 XXX000 Clearing the counter by the program (TBTC: TBR = “0”) Clock supplied to the buzzer output X: Any value.

  • Page 170: Program Example For Timebase Timer

    5.7 Program Example for Timebase Timer Program Example for Timebase Timer This section gives a program example for the timebase timer. Program Example for Timebase Timer Processing description Generates repeated interval timer interrupts at 2 : main clock source oscillation) intervals.
  • Page 171 CHAPTER 5 TIMEBASE TIMER XCHW PUSHW User processing POPW XCHW POPW RETI ENDS ;--------------------------------------------------------------------------------------------------------------------------------------------------------------...

  • Page 172: Chapter 6 Watchdog Timer

    CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer. 6.1 Overview of Watchdog Timer 6.2 Structure of Watchdog Timer 6.3 Watchdog Timer Control Register (WDTC) 6.4 Operation of Watchdog Timer 6.5 Notes on Using Watchdog Timer 6.6 Program Example for Watchdog Timer...

  • Page 173: Overview Of Watchdog Timer

    CHAPTER 6 WATCHDOG TIMER Overview of Watchdog Timer The watchdog timer is a 1-bit counter that uses either output from the timebase timer operating with the main clock or from the watch prescaler operating with the subclock. The watchdog timer resets the CPU if not cleared within a fixed time after activation. Watchdog Timer Function The watchdog timer is a counter provided to guard against program runaway.

  • Page 174: Structure Of Watchdog Timer

    6.2 Structure of Watchdog Timer Structure of Watchdog Timer The watchdog timer consists of the following six blocks: • Count clock selector • Watchdog timer counter • Reset controller • Watchdog timer clear selector • Counter clear controller • Watchdog timer control register (WDTC) Block Diagram of Watchdog Timer Figure 6.2-1 Block Diagram of Watchdog Timer Watchdog control register (WDTC)
  • Page 175 CHAPTER 6 WATCHDOG TIMER Reset controller Generates a reset signal to the CPU when an overflow occurs on the watchdog timer counter. Watchdog timer clear selector Selects the watchdog timer clear signal from the timebase timer or watch prescaler at the same time as when the count clock is selected.

  • Page 176: Watchdog Timer Control Register (Wdtc)

    6.3 Watchdog Timer Control Register (WDTC) Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) is used to select the count clock and to activate or clear the watchdog timer. Watchdog Timer Control Register (WDTC) Figure 6.3-1 Watchdog Timer Control Register (WDTC) Address Bit 7 Bit 6...
  • Page 177 CHAPTER 6 WATCHDOG TIMER Table 6.3-1 Watchdog Timer Control Register (WDTC) Bits (Continued) Function Bit 6 • The read value is indeterminate. Bit 5 Unused bits • Writing to these bits has no effect on the operation. Bit 4 • Writing "0101 "...

  • Page 178: Operation Of Watchdog Timer

    6.4 Operation of Watchdog Timer Operation of Watchdog Timer The watchdog timer generates a watchdog reset when the watchdog timer counter overflows. Watchdog Timer Operation Activating watchdog timer " to the watchdog control bits in the • The watchdog timer is activated by writing "0101 watchdog control register (WDTC: WTE3 to WTE0) for the first time after a reset.

  • Page 179: Figure 6.4-1 Watchdog Timer Clear And Interval Time

    CHAPTER 6 WATCHDOG TIMER Figure 6.4-1 shows the relationship between the watchdog timer clear timing and the interval time when the timebase timer output is used as the count clock (at main clock oscillation of 4.2 MHz). Figure 6.4-1 Watchdog Timer Clear and Interval Time Minimum time 998.6 ms Count clock output of...

  • Page 180: Notes On Using Watchdog Timer

    6.5 Notes on Using Watchdog Timer Notes on Using Watchdog Timer This section lists points to note when using the watchdog timer. Notes on Using Watchdog Timer Stopping watchdog timer Once activated, the watchdog timer can not stop until a reset generates. Selecting the count clock The count clock select bit (WDTC: CS) can be updated only when the watchdog timer control bits (WDTC: WTE3 to WTE0) are set to "0101...

  • Page 181: Program Example For Watchdog Timer

    CHAPTER 6 WATCHDOG TIMER Program Example for Watchdog Timer This section gives a program example for the watchdog timer. Program Example for Watchdog Timer Processing description • Selects watch prescaler as a count clock and activates the watchdog timer immediately after the program.
  • Page 182 6.6 Program Example for Watchdog Timer MAIN ; The loop must be executed in less than the minimum interval time of the watchdog timer. ENDS ;----------------------------------------------------------------------------------------------------------------------------------------------------------------...
  • Page 183 CHAPTER 6 WATCHDOG TIMER...

  • Page 184: Chapter 7 8/16-Bit Timer/Counter

    CHAPTER 7 8/16-BIT TIMER/COUNTER This chapter describes the functions and operation of the 8/16-bit timer/counter. 7.1 Overview of 8/16-bit Timer/Counter 7.2 Structure of 8/16-bit Timer/Counter 7.3 8/16-bit Timer/Counter Pin 7.4 8/16-bit Timer/Counter Registers 7.5 8/16-bit Timer/Counter Interrupts 7.6 Operation of Interval Timer Function 7.7 Operation of Counter Function 7.8 Operation of Square Wave Output Initialization Function 7.9 Stop and Restart Operations of 8/16-bit Timer/Counter...

  • Page 185: Overview Of 8/16-Bit Timer/Counter

    CHAPTER 7 8/16-BIT TIMER/COUNTER Overview of 8/16-bit Timer/Counter The 8/16-bit timer/counter consists of two 8-bit counters (timer 1 and timer 2) that can be used either separately (in 8-bit mode) or in series (in 16-bit mode). Timer 1 selectively provides either the interval timer function for incrementing the count in synchronization with one of three different internal count clocks or the counter function for incrementing the count in synchronization with the clock input through an external pin.

  • Page 186: Table 7.1-2 Interval Time Ranges Of Timer 2 In 8-Bit Mode

    7.1 Overview of 8/16-bit Timer/Counter Table 7.1-2 Interval Time Ranges of Timer 2 in 8-bit Mode Count clock cycle Interval time to 2 inst inst inst Internal count clock 32 t to 2 inst inst inst 512 t to 2 inst inst inst...
  • Page 187 CHAPTER 7 8/16-BIT TIMER/COUNTER • The 16-bit timer can increment the count up to 2 • The counter function can be used in the same way as the interval timer function by using input of the external clock operating in a constant cycle.

  • Page 188: Structure Of 8/16-Bit Timer/Counter

    7.2 Structure of 8/16-bit Timer/Counter Structure of 8/16-bit Timer/Counter The 8/16-bit timer/counter consists of the following five blocks: • Count clock selectors 1 and 2 • Counter circuits 1 and 2 • Square wave output controller • Timer data registers (T1DR and T2DR) •...
  • Page 189 CHAPTER 7 8/16-BIT TIMER/COUNTER Count clock selectors 1 and 2 Count clock selectors 1 and 2 are circuits for selecting an input clock. For timer 1 in 8-bit mode or the 16-bit timer, the input can be selected from among three different internal clocks and one external clock as well.

  • Page 190: 8/16-Bit Timer/Counter Pins

    7.3 8/16-bit Timer/Counter Pins 8/16-bit Timer/Counter Pins This section describes the pins, and pin block diagram of the 8/16-bit timer/counter. 8/16-bit Timer/Counter Pins The 8/16-bit timer/counter uses the P33/EC/SCO and P34/TO/INT0 pins. P33/EC/SCO pin The P33/EC/SCO pin serves as a general-purpose I/O port pin (P33), timer external-clock input pin (EC), or as peripheral control clock output pin (SCO).

  • Page 191: Figure 7.3-1 Block Diagram Of 8/16-Bit Timer/Counter Pin (P33/Ec/Sco)

    CHAPTER 7 8/16-BIT TIMER/COUNTER Block Diagram of 8/16-bit Timer/Counter Pins Figure 7.3-1 Block Diagram of 8/16-bit Timer/Counter Pin (P33/EC/SCO) Pull-up resistor Peripheral output (optional) Approx. 50 k /5.0 V External clock input PDR (Port data register) Output enable Stop or watch mode PDR read (SPL=1) P-ch...

  • Page 192: 8/16-Bit Timer/Counter Registers

    7.4 8/16-bit Timer/Counter Registers 8/16-bit Timer/Counter Registers This section describes the 8/16-bit timer counter registers. 8/16-bit Timer/Counter Registers Figure 7.4-1 8/16-bit Timer/Counter Registers T1CR (Timer 1 control register) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value...

  • Page 193: Timer Control 1 Register (T1Cr)

    CHAPTER 7 8/16-BIT TIMER/COUNTER 7.4.1 Timer Control 1 Register (T1CR) The timer 1 control register (T1CR) is used to select each function of timer 1 in 8-bit mode or of the 16-bit timer, enable or disable operation, control interrupts, and check the state of the 8/16-bit timer/counter.

  • Page 194: Table 7.4-1 Timer 1 Control Register (T1Cr) Bits

    7.4 8/16-bit Timer/Counter Registers Table 7.4-1 Timer 1 Control Register (T1CR) Bits Function • In 8-bit mode This bit is set to "1" when the counter value in timer 1 matches the value (comparate data latch) set in the timer 1 data register (T1DR). •...
  • Page 195 CHAPTER 7 8/16-BIT TIMER/COUNTER Table 7.4-1 Timer 1 Control Register (T1CR) Bits (Continued) Function • This bit activates or stops the counter. • Setting this bit to "1" from "0" clears the counter. If the timer is operating continuously (T1STP = "0") at this time, the counter starts T1STR: Bit 0 operation to increment the count in synchronization with the selected...

  • Page 196: Timer Control 2 Register (T2Cr)

    7.4 8/16-bit Timer/Counter Registers 7.4.2 Timer Control 2 Register (T2CR) The timer 2 control register (T2CR) is used to select each function of timer 1 in 8-bit mode or of the 16-bit timer, enable or disable operation, control interrupts, and check the state of the 8/16-bit timer/counter.

  • Page 197: Table 7.4-2 Timer 2 Control Register (T2Cr) Bits

    CHAPTER 7 8/16-BIT TIMER/COUNTER Table 7.4-2 Timer 2 Control Register (T2CR) Bits Function • This bit is set to "1" when the counter value in timer 2 matches the value (comparate data latch) set in the timer 2 data register (T2DR). •...

  • Page 198: Timer 1 Data Register (T1Dr)

    7.4 8/16-bit Timer/Counter Registers 7.4.3 Timer 1 Data Register (T1DR) The timer 1 data register (T1DR) is used to set the interval timer value (for the interval timer function) or counter value (for the counter function) either for timer 1 in 8-bit mode or for the lower eight bits of the 16-bit timer.
  • Page 199 CHAPTER 7 8/16-BIT TIMER/COUNTER In 16-bit mode The value in the T1DR register is compared to the counter value in the lower eight bits of the 16-bit timer. The register sets the lower eight bits of the interval time when the interval timer function is used;...

  • Page 200: Timer 2 Data Register (T2Dr)

    7.4 8/16-bit Timer/Counter Registers 7.4.4 Timer 2 Data Register (T2DR) The timer 2 data register (T2DR) is used to set the interval timer value (for the interval timer function) or counter value (for the counter function) either for timer 2 in 8-bit mode or for the upper eight bits of the 16-bit timer.
  • Page 201 CHAPTER 7 8/16-BIT TIMER/COUNTER Tip: The value set in the T1DR, T2DR register during operation of the interval timer is calculated from the equation below. Note, however, that the instruction cycle depends on the clock mode and gear function. 16-bit data value = interval time/(count clock cycle ? instruction cycle) - 1 The upper and lower eight bits of the 16-bit data value are set in the T2DR and T1DR registers, respectively.

  • Page 202: 8/16-Bit Timer/Counter Interrupts

    7.5 8/16-bit Timer/Counter Interrupts 8/16-bit Timer/Counter Interrupts Whether the 8/16-bit timer/counter serves as an interval timer or counter, it generates an interrupt request when the data register and count values match. 8/16-bit Timer/Counter Interrupts Table 7.5-1 lists the interrupt request flag bit, interrupt request output enable bit, and interrupt source of the 8/16-bit timer/counter.

  • Page 203: Table 7.5-2 Register And Vector Table For 8/16-Bit Timer/Counter Interrupt

    CHAPTER 7 8/16-BIT TIMER/COUNTER Register and Vector Table for 8/16-bit Timer/Counter Interrupt Table 7.5-2 Register and Vector Table for 8/16-bit Timer/Counter Interrupt Interrupt level setting register Vector table address Interrupt Register Setting bits Upper Lower IRQ3 ILR1 (007C L31 (Bit 7) L30 (Bit 6) FFF4 FFF5...

  • Page 204: Operation Of Interval Timer Function

    7.6 Operation of Interval Timer Function Operation of Interval Timer Function This section describes the operation of the interval timer function of the 8/16-bit timer/ counter. Operation of Interval Timer Function In 8-bit mode Figure 7.6-1 illustrates the settings required to operate timer 1 as an interval timer in 8-bit mode. Figure 7.6-1 Settings for Interval Timer Function (Timer 1) Bit 7 Bit 6...

  • Page 205: Figure 7.6-3 Operation Of Interval Timer Function (Timer 1) In 8-Bit Mode

    CHAPTER 7 8/16-BIT TIMER/COUNTER Figure 7.6-3 illustrates the operation of the interval timer function in 8-bit mode. Figure 7.6-3 Operation of Interval Timer Function (Timer 1) in 8-bit Mode Compared value Counter value Compared value (FF Time Change of T1DR value ®...

  • Page 206: Operation Of Counter Function

    7.7 Operation of Counter Function Operation of Counter Function This section describes the operation of the counter function of the 8/16-bit timer/ counter. Operation of Counter Function In 8-bit mode Figure 7.7-1 illustrates the settings required to operate timer 1 as a counter in 8-bit mode. Figure 7.7-1 Settings for Counter Function (in 8-bit Mode) Bit 7 Bit 6...

  • Page 207: Figure 7.7-2 Settings For Counter Function (In 16-Bit Mode)

    CHAPTER 7 8/16-BIT TIMER/COUNTER In 16-bit mode Figure 7.7-2 illustrates the settings required to use the counter function in 16-bit mode. Figure 7.7-2 Settings for Counter Function (in 16-bit Mode) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...

  • Page 208: Figure 7.7-3 Operation Of Counter Functions In 16-Bit Mode

    7.7 Operation of Counter Function Figure 7.7-3 illustrates operations of the counter function in 16-bit mode. Figure 7.7-3 Operation of Counter Functions in 16-bit Mode External clock Counter cleared T1STR bit (T1STP = “0”) 1388 0000 0001 Counter value 0000 0001 0002 0003...

  • Page 209: Operation Of Square Wave Output Initialization Function

    CHAPTER 7 8/16-BIT TIMER/COUNTER Operation of Square Wave Output Initialization Function The square wave output (TO) can be set to an arbitrary initial value with the timer 1 control register (T1CR). Operation of Square Wave Output Initialization Function (Timer 1) The square wave output can be set to an arbitrary initial value by software only when the timer stops operation (T1CR: T1STR = "0").

  • Page 210: Figure 7.8-2 Initial Setup Operation Of The Square Wave Output

    7.8 Operation of Square Wave Output Initialization Function Figure 7.8-2 illustrates initial setup operation of the square wave output. Figure 7.8-2 Initial setup operation of the square wave output Port* Timer* Pin state P34/TO/INT0 Set value Undefined Square wave output (initial value) *1: When the T1OS1 and T1OS0 bits in the T1CR register are “00 ”, the P34/TO/INT0 pin serves as a general-purpose...

  • Page 211: Stop And Restart Operations Of 8/16-Bit Timer/Counter

    CHAPTER 7 8/16-BIT TIMER/COUNTER Stop and Restart Operations of 8/16-bit Timer/Counter This section describes the stop and restart operations of the 8/16-bit timer/counter. Stop and Restart of Timer Although the following description is for timer 1, it also applies to timer 2 in the same way. The timer stop bit (T1STP) and timer start bit (T1STR) in the timer 1 control register (T1CR) are used to stop and restart timer 1.

  • Page 212: States In Each Mode During 8/16-Bit Timer/Counter Operation

    7.10 States in Each Mode during 8/16-bit Timer/Counter Operation 7.10 States in Each Mode during 8/16-bit Timer/Counter Operation This section describes the operation of the 8/16-bit timer/counter when the device changes to sleep or stop mode or an operation halt request occurs during operation. Operation during Subclock Mode, Standby Mode, or Operation Halt Figure 7.10-1 shows the counter value state when the device changes to sleep or stop mode, or when an operation stop request occurs, during operation of the interval timer function or counter...

  • Page 213: Figure 7.10-1 Counter Operation During Subclock Or Standby Modes And Operation Halt

    CHAPTER 7 8/16-BIT TIMER/COUNTER Figure 7.10-1 Counter Operation during Subclock or Standby Modes and Operation Halt Counter value Data register set value 0000 Time Activate Match Match Match Match Match Counter cleared T1STR bit Cleared by program T1IF bit (T1IE bit) TO pin Sleep SLP bit...

  • Page 214: 7.11 Notes On Using 8/16-Bit Timer/Counter

    7.11 Notes on Using 8/16-bit Timer/Counter 7.11 Notes on Using 8/16-bit Timer/Counter This section lists points to note when using the 8/16-bit timer/counter. Notes on Using 8/16-bit Timer/Counter Notes on stopping the timer Although the following description is for timer 1, it also applies to timer 2 in the same way. The counter value is incremented by "1"...

  • Page 215: Figure 7.11-2 Error On Starting Counter Operation

    CHAPTER 7 8/16-BIT TIMER/COUNTER Figure 7.11-2 shows the error that occurs on starting counter operation. Figure 7.11-2 Error on Starting Counter Operation Counter value Count clock One cycle Cycle of Error count 0 Counter activated Using a single 8-bit channel To use only timer 1 in the 8/16-bit timer/counter in 8-bit mode, set the timer count clock select bits (T2CS1 and T2CS0) in the timer 2 control register (T2CR) to a value other than "11 "...

  • Page 216: 7.12 Program Examples For 8/16-Bit Timer/Counter

    7.12 Program Examples for 8/16-bit Timer/Counter 7.12 Program Examples for 8/16-bit Timer/Counter This section gives program examples for the 8/16-bit timer/counter. Program Example for Interval Timer Function Processing description • Repeatedly generates 20 ms interval timer interrupts, when using only the timer 1 in 8-bit mode.
  • Page 217 CHAPTER 7 8/16-BIT TIMER/COUNTER T2CR, #00000010B ; Clear timer 2 interrupt request flag, ; disable interrupt request output, set other than 16-bit mode, ; and stop operation T2CR, #00011000B ; Clear timer 1 interrupt request flag, set square wave initial value ;...
  • Page 218 7.12 Program Examples for 8/16-bit Timer/Counter Program Example for Pulse Counter Function Processing description • Generates an interrupt for every 5000 (1388 ) external clock pulses input to the EC pin using timers 1 and 2 in 16-bit mode. • The following coding example is a sample program for reading a 16-bit counter value during operation of the counter.
  • Page 219 CHAPTER 7 8/16-BIT TIMER/COUNTER SETI ; Enable for CPU interrupts. -----Data read routine--------------------------------------------------------------------------------------------------------------------------------- READ16 MOVW A, T2DR ; Read 16-bit value from T1DR and T2DR. MOVW A, T2DR ; Read 16-bit value from T1DR and T2DR ; and store old value in T register. CMPW ;...

  • Page 220: Chapter 8 8-Bit Serial I/O

    CHAPTER 8 8-BIT SERIAL I/O This chapter describes the functions and operation of the 8-bit serial I/O. 8.1 Overview of 8-bit Serial I/O 8.2 Structure of 8-bit Serial I/O 8.3 8-bit Serial I/O Pins 8.4 8-bit Serial I/O Registers 8.5 8-bit Serial I/O Interrupts 8.6 Operation of Serial Output 8.7 Operation of Serial Input 8.8 States in Each Mode during 8-bit Serial I/O Operation...

  • Page 221: Overview Of 8-Bit Serial I/O

    CHAPTER 8 8-BIT SERIAL I/O Overview of 8-bit Serial I/O The 8-bit serial I/O function is the serial transfer of 8-bit data, synchronized with the shift clock. The shift clock can be selected one clock from one external and three internal clocks.

  • Page 222: Structare Of 8-Bit Serial I/O

    8.2 Structare of 8-bit Serial I/O Structare of 8-bit Serial I/O Each channel of the 8-bit serial I/O consists of the following 5 blocks: • Shift clock controller • Shift clock counter • Serial data register (SDR) • Serial mode register (SMR) •...
  • Page 223 CHAPTER 8 8-BIT SERIAL I/O Shift clock control circuit Selects the shift clock from one external and three internal clocks. If an internal shift clock is selected, the shift clock can be output to the SCK pin. If the external shift clock is selected, the clock input from the SCK pin is used as the shift clock.

  • Page 224: 8-Bit Serial I/O Pins

    8.3 8-bit Serial I/O Pins 8-bit Serial I/O Pins This section describes the pins and pin block diagram of 8-bit serial I/O. 8-bit Serial I/O Pins 8-bit serial I/O uses the P32/SI, P31/SO, and P30/SCK pins. P32/SI pin The P32/SI pin can function either as a general-purpose I/O port (P32) or as the serial data input pin (hysteresis input) for 8-bit serial I/O (SI).

  • Page 225: Figure 8.3-1 Block Diagram Of 8-Bit Serial I/O Pins

    CHAPTER 8 8-BIT SERIAL I/O Block Diagram of 8-bit Serial I/O Pins Figure 8.3-1 Block Diagram of 8-bit Serial I/O Pins Pull-up resistor From output (optional) (SO and SCK pins only) Approx. 50 k /5.0 V To input (SI and SCK pins only) (Port data register) From the output enable bit...

  • Page 226: 8-Bit Serial I/O Registers

    8.4 8-bit Serial I/O Registers 8-bit Serial I/O Registers This section describes the 8-bit serial I/O registers. 8-bit Serial I/O Registers Figure 8.4-1 8-bit Serial I/O-1 Registers SMR (Serial mode register) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

  • Page 227: Serial Mode Register (Smr)

    CHAPTER 8 8-BIT SERIAL I/O 8.4.1 Serial Mode Register (SMR) The serial mode register (SMR) is used to enable or disable serial I/O operation, select the shift clock, set the transfer direction, control interrupts, and check the state of 8-bit serial I/O.

  • Page 228: Table 8.4-1 Serial Mode Register (Smr) Bits

    8.4 8-bit Serial I/O Registers Table 8.4-1 Serial Mode Register (SMR) Bits Function • This bit is set to "1" when the serial output operation has output 8 bits of serial data or the serial input operation has input 8 bits of SIOF: serial data.
  • Page 229 CHAPTER 8 8-BIT SERIAL I/O Table 8.4-1 Serial Mode Register (SMR) Bits (Continued) Function • This bit controls serial I/O transfer start and transfer enable. This bit can also be used to determine whether transfer has completed. • Writing "1" to this bit when an internal shift clock is selected (CKS1, ") clears the shift clock counter and starts CKS0 = other than "11 data transfer.

  • Page 230: Serial Data Register (Sdr)

    8.4 8-bit Serial I/O Registers 8.4.2 Serial Data Register (SDR) The serial data register (SDR) stores the transfer data for 8-bit serial I/O. The register functions as the transmit data register for serial output operation and as the receive data register for serial input operation. Serial Data Register (SDR) Figure 8.4-3 shows the bit structure of the serial data register.

  • Page 231: 8-Bit Serial I/O Interrupts

    CHAPTER 8 8-BIT SERIAL I/O 8-bit Serial I/O Interrupts The 8-bit serial I/O can generate interrupt requests after completion of the serial input and output of the 8-bit data. Interrupt during Serial I/O Operation The 8-bit serial I/O performs the serial input operation and serial output operation at the same time.

  • Page 232: Operation Of Serial Output

    8.6 Operation of Serial Output Operation of Serial Output The 8-bit serial I/O can perform serial output of 8-bit data synchronized with a shift clock. Serial Output Operation Serial output can operate using an internal or external shift clock. When serial input and output operation is enabled, the contents of the SDR register are output to the serial data output pin (SO) at the same time that serial input is performed.

  • Page 233: Figure 8.6-3 8-Bit Serial Output Operation

    CHAPTER 8 8-BIT SERIAL I/O Figure 8.6-3 shows the 8-bit serial output operation. Figure 8.6-3 8-bit Serial Output Operation For LSB first Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO pin Serial output data Shift clock...

  • Page 234: Operation Of Serial Input

    8.7 Operation of Serial Input Operation of Serial Input The 8-bit serial I/O can perform serial input of 8-bit data synchronized with a shift clock. Serial Input Operation Serial input can operate using an internal or external shift clock. When serial input and output operation is enabled, the contents of the SDR register are output to the serial data output pin (SO) at the same time that serial input is performed.

  • Page 235: Figure 8.7-3 8-Bit Serial Input Operation

    CHAPTER 8 8-BIT SERIAL I/O data (idle state). Figure 8.7-3 shows the 8-bit serial input operation. Figure 8.7-3 8-bit Serial Input Operation For MSB first Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SI pin Serial input data...

  • Page 236: States In Each Mode During 8-Bit Serial I/O Operation

    8.8 States in Each Mode during 8-bit Serial I/O Operation States in Each Mode during 8-bit Serial I/O Operation This section describes the operation of the 8-bit serial I/O when the device changes to sleep mode, or to stop or watch mode, or when the operation halts, during the serial I/O operation.

  • Page 237: Figure 8.8-3 Operation During Halt (Internal Shift Clock)

    CHAPTER 8 8-BIT SERIAL I/O Operation during halt Halting operation during transfer (SMR: SST = "0") halts the transfer and clears the shift clock counter, as shown in Figure 8.8-3. Therefore, the device being communicated with must also be initialized. In serial output operation, set data to the SDR register again before reactivating. Figure 8.8-3 Operation during Halt (Internal Shift Clock) SCK output SST bit...

  • Page 238: Figure 8.8-5 Operation In Stop Or Watch Mode (External Shift Clock)

    8.8 States in Each Mode during 8-bit Serial I/O Operation Operation in stop or watch mode In stop or watch mode, serial I/O operation halts and transfer aborts, as shown in Figure 8.8-5. After wake-up from stop or watch mode,operation restarts from the point where it halted . This causes an error to occur on the device with which the 8-bit serial I/O is communicating.

  • Page 239: Notes On Using 8-Bit Serial I/O

    CHAPTER 8 8-BIT SERIAL I/O Notes on Using 8-bit Serial I/O This section lists points to note when using the 8-bit serial I/O. Notes on Using 8-bit Serial I/O Error on starting serial transfer As activating the serial transfer by software (SMR: SST = "1") is not synchronized with the falling edge (output) or rising edge (input) of the shift clock, there is a delay of up to one cycle of the selected shift clock before the first serial data I/O occurs.

  • Page 240: 8.10 Connection Example For 8-Bit Serial I/O

    8.10 Connection Example for 8-bit Serial I/O 8.10 Connection Example for 8-bit Serial I/O This section shows an example of connecting together two MB89120/120A series 8-bit serial I/Os and performing bidirectional serial I/O. Performing Bidirectional Serial I/O Figure 8.10-1 Connection Example for 8-bit Serial I/O (Interface between Two MB89120/120As) SIO-A SIO-B Output...

  • Page 241: Figure 8.10-2 Bidirectional Serial I/O Operation

    CHAPTER 8 8-BIT SERIAL I/O Figure 8.10-2 Bidirectional Serial I/O Operation SIO-A SIO-B Start Start Halt operation of SIO-A Halt operation of SIO-B (SST=“0”) (SST=“0”) Set the SI pin as the serial data input Set the SI pin as the serial data input (input port).

  • Page 242: 8.11 Program Examples For 8-Bit Serial I/O

    8.11 Program Examples for 8-bit Serial I/O 8.11 Program Examples for 8-bit Serial I/O This section gives program examples for 8-bit serial I/O. Program Example for Serial Output Processing description • Outputs 8 bits of serial data (55H) from the SO pin of serial I/O, then generates an interrupt when transfer is completed.
  • Page 243 CHAPTER 8 8-BIT SERIAL I/O CLRB ; Stop serial I/O transfer. ILR2,#11111101B ; Set interrupt level (level 1). SDR,#55H ; Set transfer data (55H). SMR,#01111000B ; Clear interrupt request flag, enable interrupt request output, enable shift clock output (SCK), enable serial data output (SO), select 32 tinst, LSB first.
  • Page 244 8.11 Program Examples for 8-bit Serial I/O Program Example for Serial Input Processing description • Inputs 8 bits of serial data from the SI pin of serial I/O, then generates an interrupt when transfer is completed. • The interrupt processing routine reads the transferred data and continues input. •...
  • Page 245 CHAPTER 8 8-BIT SERIAL I/O ;-----Interrupt processing routine----------------------------------------------------------------------------------------------------------------------- WARI CLRB SIOF ; Clear interrupt request flag. PUSHW XCHW PUSHW A,SDR ; Read transfer data. SETB ; Enable serial I/O transfer. User processing POPW XCHW POPW RETI ENDS ;----------------------------------------------------------------------------------------------------------------------------------------------------------------...

  • Page 246: Chapter 9 Buzzer Output

    CHAPTER 9 BUZZER OUTPUT This chapter describes the functions and operation of the buzzer output. 9.1 Overview of Buzzer Output 9.2 Structure of Buzzer Output 9.3 Buzzer Output Pins 9.4 Buzzer Output Register 9.5 Program Example for Buzzer Output...

  • Page 247: Overview Of Buzzer Output

    CHAPTER 9 BUZZER OUTPUT Overview of Buzzer Output The buzzer output can select from seven different output frequencies (square waves) and can be used for applications such as sounding a buzzer to confirm key input. The output pin also serves for remote-control transmission frequency output. Buzzer Output Function The buzzer output function outputs a signal (square wave) suitable for applications such as sounding a buzzer to confirm an operation.
  • Page 248 9.1 Overview of Buzzer Output Tip: Calculation example for output frequency For a 4.2 MHz main clock source oscillation (F ) and if the buzzer register (BZCR) selects the timebase timer divided output cycle of F (BZ2, BZ1, BZ0 = "011 "), the output frequency of the BZ pin is calculated as follows: Output frequency...

  • Page 249: Structure Of Buzzer Output

    CHAPTER 9 BUZZER OUTPUT Structure of Buzzer Output The buzzer output consists of the following two blocks: • Buzzer output selector • Buzzer register (BZCR) Block Diagram of Buzzer Output Figure 9.2-1 Block Diagram of Buzzer Output Internal data bus Buzzer register (BZCR) –...

  • Page 250: Buzzer Output Pin

    9.3 Buzzer Output Pin Buzzer Output Pin This section describes the pin and pin block diagram of the buzzer output. Buzzer Output Pin The buzzer output uses the P37/BZ/(RCO) pin. P37/BZ/(RCO) pin The P37/BZ/(RCO) pin serves as a general-purpose I/O port pin (P37), remote-control transmission frequency output pin (RCO), or as buzzer output pin (BZ).

  • Page 251: Buzzer Output Register

    CHAPTER 9 BUZZER OUTPUT Buzzer Output Register This section describes the buzzer output register. Buzzer Output Register Figure 9.4-1 Buzzer Output Register BZCR (Buzzer register) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 000F...

  • Page 252: Buzzer Register (Bzcr)

    9.4 Buzzer Output Register 9.4.1 Buzzer Register (BZCR) The buzzer register (BZCR) is used to select the buzzer output frequency and also to enable buzzer output. Buzzer Register (BZCR) Figure 9.4-2 Buzzer Register (BZCR) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
  • Page 253 CHAPTER 9 BUZZER OUTPUT Table 9.4-1 Buzzer Register (BZCR) Bits (Continued) Function These bits select the buzzer output and enable output. • Setting "000 " to these bits disables the buzzer output and sets the pin as a general-purpose port (P37) or remote-control transmission frequency output pin (RCO).

  • Page 254: Program Example For Buzzer Output

    9.5 Program Example for Buzzer Output Program Example for Buzzer Output This section gives a program example for the buzzer output. Example Program for Buzzer Output Processing description • Outputs a buzzer output of approximately 1.025 kHz to the BZ pin, then turns the buzzer output "OFF".
  • Page 255 CHAPTER 9 BUZZER OUTPUT...

  • Page 256: Chapter 10 External Interrupt Circuit 1 (Edge)

    CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) This chapter describes the functions and operation of the external interrupt circuit 1 (edge). 10.1 Overview of External Interrupt Circuit 1 (Edge) 10.2 Structure of External Interrupt Circuit 1 10.3 External Interrupt Circuit 1 Pins 10.4 External Interrupt Circuit 1 Register 10.5 External Interrupt Circuit 1 Interrupts 10.6 Operation of External Interrupt Circuit 1...

  • Page 257: Overview Of External Interrupt Circuit 1 (Edge)

    CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 10.1 Overview of External Interrupt Circuit 1 (Edge) The external interrupt circuit 1 detects edges on the signals input to the three external interrupt pins and generates the corresponding interrupt requests to the CPU. External Interrupt Circuit 1 Function (Edge Detection) The external interrupt circuit 1 function detects the specified edges on signals input to the external interrupt pins and to generate interrupt requests to the CPU.

  • Page 258: Structure Of External Interrupt Circuit 1

    10.2 Structure of External Interrupt Circuit 1 10.2 Structure of External Interrupt Circuit 1 The external interrupt circuit 1 consists of three blocks, each with the same interrupt functions. Each block contains the following two elements: • Edge detectors (0 to 2) •...
  • Page 259 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) Interrupt requests from external interrupt circuit 1 IRQ0: This interrupt request is generated if interrupt request output has been enabled (EIC1: EIE0 = "1") when a edge with a selected polarity is input to the external interrupt input pin INT0.

  • Page 260: 10.3 External Interrupt Circuit 1 Pins

    10.3 External Interrupt Circuit 1 Pins 10.3 External Interrupt Circuit 1 Pins This section describes the pins and pin block diagram of the external interrupt circuit External Interrupt Circuit 1 Pins The external interrupt circuit 1 uses P34/TO/INT0, P35/INT1, and P36/INT2 pins. P34/TO/INT0 pin The P34/TO/INT0 pin serves as a general-purpose I/O port pin (P34), 8/16-bit timer/counter square wave output pin (TO), or as external interrupt input (hysteresis) pin (INT0).

  • Page 261: Figure 10.3-1 Block Diagram Of External Interrupt Circuit 1 Pins

    CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) Block Diagram of External Interrupt Circuit Pins Figure 10.3-1 Block Diagram of External Interrupt Circuit 1 Pins Pull-up resistor From rectangular wave output (optional) From output enable signal (P34 only) (P34 only) of 8/16-bit timer/counter Approx.

  • Page 262: 10.4 External Interrupt Circuit 1 Registers

    10.4 External Interrupt Circuit 1 Registers 10.4 External Interrupt Circuit 1 Registers This section describes the external interrupt circuit 1 registers. External Interrupt Circuit 1 Registers Figure 10.4-1 External Interrupt Circuit Registers EIC1 (External interrupt 1 control register) Address Bit 7 Bit 6 Bit 5 Bit 4...

  • Page 263: External Interrupt 1 Control Register 1 (Eic1)

    CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 10.4.1 External Interrupt 1 Control Register 1 (EIC1) The external interrupt 1 control register 1 (EIC1) is used to select the edge polarity for external interrupt pins (INT0, INT1) and to control interrupts. External Interrupt 1 Control Register 1 (EIC1) Figure 10.4-2 External Interrupt 1 Control Register 1 (EIC1) Address...

  • Page 264: Table 10.4-1 External Interrupt 1 Control Register 1 (Eic1) Bits

    10.4 External Interrupt Circuit 1 Registers Table 10.4-1 External Interrupt 1 Control Register 1 (EIC1) Bits Function • This bit is set to "1" when the edge selected by the edge polarity selection EIR1: bit 1 (SL10, SL11) is input to an external interrupt pin (INT1). External •...

  • Page 265: External Interrupt 1 Control Register 2 (Eic2)

    CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 10.4.2 External Interrupt 1 Control Register 2 (EIC2) The external interrupt 1 control register 2 (EIC2) is used to select the edge polarity and to control interrupts for external interrupt pin (INT2). External Interrupt 1 Control Register 2 (EIC2) Figure 10.4-3 External Interrupt 1 Control Register 2 (EIC2) Address Bit 7...
  • Page 266 10.4 External Interrupt Circuit 1 Registers Table 10.4-2 External Interrupt 1 Control Register 2 (EIC2) Bits (Continued) Function • This bit selects the edge polarity that triggers interrupts when SL21, SL20: detected on pulses input to external interrupt pin INT2. Bit 2 Edge polarity •...

  • Page 267: 10.5 External Interrupt Circuit 1 Interrupts

    CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 10.5 External Interrupt Circuit 1 Interrupts The external interrupt circuit 1 can generate interrupt requests when it detects a specified edge on the signal input to an external interrupt pin. Interrupts for External Interrupt Circuit 1 Operation When a specified edge on an external interrupt input is detected, corresponding external interrupt request flag bit (EIC1, EIC2: EIR0 to EIR2) is set to "1".

  • Page 268: Operation Of External Interrupt Circuit 1

    10.6 Operation of External Interrupt Circuit 1 10.6 Operation of External Interrupt Circuit 1 The external interrupt circuit 1 can detect a specified edge on a signal input to an external interrupt pin. Operation of External Interrupt Circuit 1 Figure 10.6-1 shows the settings required to operate the external interrupt circuit. Figure 10.6-1 External Interrupt Circuit 1 Settings Bit 7 Bit 6...

  • Page 269: Figure 10.6-2 External Interrupt (Int0) Operation

    CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) Figure 10.6-2 External Interrupt (INT0) Operation Input waveform to the INT0 pin Interrupt request flag bit Cleared at the same time as the EIE0 bit is set. cleared by the program. EIR0 bit EIE0 bit SL01 bit SL00 bit...

  • Page 270: Program Example For External Interrupt Circuit 1

    10.7 Program Example for External Interrupt Circuit 1 10.7 Program Example for External Interrupt Circuit 1 This section gives a program example for the external interrupt circuit 1. Program Example for External Interrupt Circuit 1 Processing description • Generates interrupts on detecting a rising edge on pulses input to the INT0 pin. Coding example DDR3 000DH...
  • Page 271 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) SETI ; Enable interrupts. ;-----Interrupt processing routine---------------------------------------------------------------------------------------------------------------------- WARI CLRB EIR0 ; Clear external interrupt request flag. PUSHW XCHW PUSHW User processing POPW XCHW POPW RETI ENDS ;----------------------------------------------------------------------------------------------------------------------------------------------------------------...

  • Page 272: Chapter 11 External Interrupt Circuit 2 (Level)

    CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) This chapter describes the functions and operation of external interrupt circuit 2 (level). This circuit is available only in the MB89120A series. 11.1 Overview of External Interrupt Circuit 2 (Level) 11.2 Structure of External Interrupt Circuit 2 11.3 External Interrupt Circuit 2 Pin 11.4 External Interrupt Circuit 2 Register 11.5 External Interrupt Circuit 2 Interrupts...

  • Page 273: Overview Of External Interrupt Circuit 2 (Level)

    CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.1 Overview of External Interrupt Circuit 2 (Level) External interrupt circuit 2 detects the levels of signals input to eight external interrupt pins and generates a single interrupt request to the CPU. (This circuit is available only in the MB89120A series.) External Interrupt Circuit 2 Function (Level Detection) External interrupt circuit 2 detects "L"...

  • Page 274: Structure Of External Interrupt Circuit 2

    11.2 Structure of External Interrupt Circuit 2 11.2 Structure of External Interrupt Circuit 2 External interrupt circuit 2 consists of the following three blocks: • Interrupt request generator • External interrupt 2 control register (EIE2) • External interrupt 2 flag register (EIF2) Block Diagram of External Interrupt Circuit 2 Figure 11.2-1 Block Diagram of External Interrupt Circuit 2 External interrupt 2 control register (EIE2)
  • Page 275 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) IRQA: This interrupt request is generated when an "L" level signal is input to any of the INT20 to INT27 external interrupt pins and when the external interrupt input enable bit corresponding to that pin is "1".

  • Page 276: 11.3 External Interrupt Circuit 2 Pins

    11.3 External Interrupt Circuit 2 Pins 11.3 External Interrupt Circuit 2 Pins This section describes the pins related to external interrupt circuit 2 and provides its pin block diagram. External Interrupt Circuit 2 Pins External interrupt circuit 2 uses eight external interrupt pins. P00/INT20 to P07/INT27 The P00/INT20 to P07/INT27 pins can function either as external interrupt input pins or as general-purpose I/O port pins.

  • Page 277: Figure 11.3-1 Block Diagram Of External Interrupt Circuit 2 Pins

    CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) Block Diagram of External Interrupt Circuit 2 Pins Figure 11.3-1 Block Diagram of External Interrupt Circuit 2 Pins Pull-up resistor To externel interrupt (optional) (MB89120A only) Approx. 50 k /5.0 V PDR (Port data register) Stop or watch mode (SPL=1) PDR read...

  • Page 278: 11.4 External Interrupt Circuit 2 Registers

    11.4 External Interrupt Circuit 2 Registers 11.4 External Interrupt Circuit 2 Registers This section describes the registers for external interrupt circuit 2. External Interrupt Circuit 2 Registers Figure 11.4-1 External Interrupt Circuit 2 Registers EIC2 (External interrupt 2 control register) Address Bit 7 Bit 6...

  • Page 279: External Interrupt 2 Control Register (Eic2)

    CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.4.1 External Interrupt 2 Control Register (EIC2) The external interrupt 2 control register (EIE2) enabls or disables the INT20 to INT27 external interrupt pins for interrupt input. External Interrupt 2 Control Register (EIE2) Figure 11.4-2 External Interrupt Circuit 2 Control Register(EIE2) Address Bit 7...

  • Page 280: Table 11.4-2 Functions Of External Interrupt 2 Control Register (Eie2) Bits

    11.4 External Interrupt Circuit 2 Registers Table 11.4-2 Functions of External Interrupt 2 Control Register (EIE2) Bits Bit name Function • These bits are used to enable or disable the the INT20 to INT27 external interrupt pins for interrupt input. •...

  • Page 281: External Interrupt 2 Flag Register (Eif2)

    CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.4.2 External Interrupt 2 Flag Register (EIF2) The external interrupt 2 flag register (EIF2) detects level interrupts and clears the interrupt request flag. External Interrupt 2 Flag Register (EIF2) Figure 11.4-3 External Interrupt 2 Flag Register (EIF2) Address Bit 7 Bit 6...

  • Page 282: 11.5 External Interrupt Circuit 2 Interrupts

    11.5 External Interrupt Circuit 2 Interrupts 11.5 External Interrupt Circuit 2 Interrupts The interrupt source of external interrupt circuit 2 is the "L" level signal input to any external interrupt pin. External Interrupt Circuit 2 Interrupts When an "L" level signal is input to any external interrupt pin enabled for external interrupt input, the external interrupt request flag bit (EIF2: IF20) is set to "1"...

  • Page 283: Operation Of External Interrupt Circuit 2

    CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.6 Operation of External Interrupt Circuit 2 The external interrupt circuit 2 can detect the "L" level of a signal input to an external interrupt pin and generates an interrupt nequest to the CPU. Operation of External Interrupt Circuit 2 Figure 11.6-1 shows the settings required to operate external interrupt circuit 2.

  • Page 284: Figure 11.6-2 Operation Of External Interrupt Circuit 2 (Int20)

    11.6 Operation of External Interrupt Circuit 2 Figure 11.6-2 shows the operation of external interrupt circuit 2 (using the INT20 pin). Figure 11.6-2 Operation of External Interrupt Circuit 2 (INT20) Waveform input to INT20 pin (“L” level detected) External interrupt input enabled EIE2:IE20 Cleared by interrupt handler EIF2:IF20...

  • Page 285: Program Example For External Interrupt Circuit 2

    CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.7 Program Example for External Interrupt Circuit 2 This section provides a program example for external interrupt circuit 2. Program Example for External Interrupt Circuit 2 Processing description Generates an interrupt on detection of an "L" level signal input to the INT20 pin. Coding example DDR0 0001H...
  • Page 286 11.7 Program Example for External Interrupt Circuit 2 WARI EIE2, #00000000B ; Disable INT20 pin for external interrupt input. CLRB IF20 ; Clear external interrupt request flag. PUSHW XCHW PUSHW User processing POPW XCHW POPW RETI ENDS ;--------------------------------------------------------------------------------------------------------------------------------------------------------------...
  • Page 287 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)

  • Page 288: Chapter 12 Watch Prescaler

    CHAPTER 12 WATCH PRESCALER This chapter describes the functions and operation of the watch prescaler. 12.1 Overview of Watch Prescaler 12.2 Structure of Watch Prescaler 12.3 Watch Prescaler Control Register (WPCR) 12.4 Watch Prescaler Interrupts 12.5 Operation of Watch Prescaler 12.6 Notes on Using Watch Prescaler 12.7 Program Example for Watch Prescaler...

  • Page 289: 12.1 Overview Of Watch Prescaler

    CHAPTER 12 WATCH PRESCALER 12.1 Overview of Watch Prescaler The watch prescaler is the 15-bit free-run counter which increments the count in synchronization with the subclock signal generated by the clock generator. The watch prescaler has the interval timer function for selecting one of four different interval times.

  • Page 290: Table 12.1-2 Clock Signals Supplied From Watch Prescaler

    12.1 Overview of Watch Prescaler Table 12.1-2 lists the cycles of clock signals supplied to peripherals from the watch prescaler. Table 12.1-2 Clock Signals Supplied from Watch Prescaler Subclock destination Subclock cycle Remarks Subclock oscillation Do not enter subclock mode during (1.00 s) stabilization delay time oscillation stabilization delay time.

  • Page 291: 12.2 Structure Of Watch Prescaler

    CHAPTER 12 WATCH PRESCALER 12.2 Structure of Watch Prescaler The watch prescaler consists of the following four blocks: • Watch prescaler counter • Counter clear circuit • Interval timer selector • Watch prescaler control register (WPCR) Block Diagram of Watch Prescaler Figure 12.2-1 Block Diagram of Watch Prescaler Watch prescaler To buzzer output...
  • Page 292 12.2 Structure of Watch Prescaler Watch prescaler control register (WPCR) The watch prescaler control register (WPCR) is used to select the interval time, clear the counter, control interrupts, and to check the watch prescaler status.

  • Page 293: Watch Prescaler Control Register (Wpcr)

    CHAPTER 12 WATCH PRESCALER 12.3 Watch Prescaler Control Register (WPCR) The watch prescaler control register (WPCR) is used to select the interval time, clear the counter, control interrupts, and to check the watch prescaler status. Watch Prescaler Control Register (WPCR) Figure 12.3-1 Watch Prescaler Control Register (WPCR) Address Bit 7...

  • Page 294: Table 12.3-1 Functions Of Watch Prescaler Control Register (Wpcr) Bits

    12.3 Watch Prescaler Control Register (WPCR) Table 12.3-1 Functions of Watch Prescaler Control Register (WPCR) Bits Bit name Function • This bit is set to "1" at the rising edge of the frequency-divided output selected for the interval timer. WIF: •...

  • Page 295: 12.4 Watch Prescaler Interrupts

    CHAPTER 12 WATCH PRESCALER 12.4 Watch Prescaler Interrupts The watch prescaler generates an interrupt request at the rising edge of the selected frequency-divided output (using the interval timer function). Interrupts (Watch Interrupts) during Operation using Interval Timer Function When the watch prescaler counter increments the count in synchronization with the subclock source oscillation and the interval timer time has passed, the watch interrupt request flag bit (WIF) in the WPCR register is set to "1"...

  • Page 296: 12.5 Operation Of Watch Prescaler

    12.5 Operation of Watch Prescaler 12.5 Operation of Watch Prescaler The watch prescaler provides the interval timer and clock supply functions. Interval Timer Operation (Watch Prescaler) Figure 12.5-1 shows the settings required to operate the watch prescaler as the interval timer. Figure 12.5-1 Interval Timer Function Settings Bit 7 Bit 6...

  • Page 297: Figure 12.5-2 Watch Prescaler Operation

    CHAPTER 12 WATCH PRESCALER Figure 12.5-2 Watch Prescaler Operation Counter value 7FFF Cleared for transition to sub-stop mode 0000 Subclock oscillation Interval cycle Subclock oscillation stabilization delay stabilization delay time time Power-on reset Counter cleared " " (optional) (WPCR: WCLR = Cleared by interrupt handler WIF bit WIE bit...

  • Page 298: 12.6 Notes On Using Watch Prescaler

    12.6 Notes on Using Watch Prescaler 12.6 Notes on Using Watch Prescaler This section gives notes on using the watch prescaler. The watch prescaler cannot be used when the single-clock option has been selected. Notes on Using Watch Prescaler Note on setting by program When the interrupt request flag bit (WPCR: WIF) is "1"...

  • Page 299: Figure 12.6-1 Effect Of Clearing Watch Prescaler On Buzzer Output

    CHAPTER 12 WATCH PRESCALER Figure 12.6-1 Effect of Clearing Watch Prescaler on Buzzer Output Counter value 001F 0010 0000 “ ” Counter cleared by program (WPCR: WCLR = Clock signal to Buzzer output This assumes that the buzzer select bits (BZ2, BZ1, BZ0) in the buzzer register (BZCR) have been set to “101”. (Output of 1024 Hz during operation at subclock oscillation divided by 32, 32.768 kHz)

  • Page 300: 12.7 Program Example For Watch Prescaler

    12.7 Program Example for Watch Prescaler 12.7 Program Example for Watch Prescaler This section provides a program example for the watch prescaler. Program Example for Watch Prescaler Processing description Repeatedly generates a watch interrupt of 2 : subclock oscillation). The time interval is 1 second (during operation at 32.768 kHz).
  • Page 301 CHAPTER 12 WATCH PRESCALER User processing POPW XCHW POPW RETI ENDS ;---------------------------------------------------------------------------------------------------------------------------------------------------------------...

  • Page 302: Chapter 13 Remote-Control Transmission Frequency Generator

    CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR This section describes the functions and operation of the remote-control transmission frequency generator. This circuit is available only in the MB89120A series. 13.1 Overview of Remote-control Transmission Frequency Generator 13.2 Structure of Remote-control Transmission Frequency Generator 13.3 Remote-control Transmission Frequency Generator Pin 13.4 Remote-control Transmission Frequency Generator Registers 13.5 Operation of Remote-control Transmission Frequency Generator...

  • Page 303: Overview Of Remote-Control Transmission Frequency Generator

    CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR 13.1 Overview of Remote-control Transmission Frequency Generator The remote-control transmission frequency generator is a 6-bit binary counter that offers a choice of four different internal count clocks, allowing the cycle and "H" width of the output waveform to be set. This circuit can therefore be used as a 6-bit PPG (programmable pulse generator).
  • Page 304 13.1 Overview of Remote-control Transmission Frequency Generator = "011110 " (30 + 1 -clock cycle) × 0.5 × 4/F = 31 × 0.475 µs = 14.725 µs "H" width = (Value compared for "H" width + 1) × 0.5 t inst = "001010 "...

  • Page 305: Table 13.1-2 Resolutions And Output Cycles Of 6-Bit Ppg

    CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR Duty ratio (value compared for "H" width +1)/(value compared for cycle +1) × 100(%) Table 13.1-2 lists the resolutions, duty ratio minimum steps, and output cycles that can be set. Table 13.1-2 Resolutions and Output Cycles of 6-bit PPG Value Setting range of Output cycle...

  • Page 306: Table 13.1-3 Resolutions And Output Cycles Of 6-Bit Ppg

    13.1 Overview of Remote-control Transmission Frequency Generator Instruction cycle inst When the value set for "H" width is equal to the value set for the cycle, the output level is always "H." 6-bit PPG Functions(In case of selecting 1/8/32 t inst The remote-control transmission frequency generator can serve as a 6-bit PPG without modification because the cycle and "H"...
  • Page 307 CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR Table 13.1-3 Resolutions and Output Cycles of 6-bit PPG (Continued) Output cycle Value Setting range Duty ratio compared of values for Resolution Count clock Count clock Count clock minimum step for cycle "H" width = 1 t = 8 t = 32 t...

  • Page 308: Structure Of Remote-Control Transmission Frequency Generator

    13.2 Structure of Remote-control Transmission Frequency Generator 13.2 Structure of Remote-control Transmission Frequency Generator The remote-control transmission frequency generator consists of the following five blocks: • Count clock selector • 6-bit counter • Comparator • Remote-control transmission frequency control register 1 (RCR1) •...
  • Page 309 CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR count clock selector. The output enable bit in the RCR2 register can be used to clear this counter (RCEN = "0"). Comparator The comparator holds the output at "H" level until the 6-bit counter value matches the value in the "H"...

  • Page 310: 13.3 Remote-Control Transmission Frequency Generator Pin

    13.3 Remote-control Transmission Frequency Generator Pin 13.3 Remote-control Transmission Frequency Generator Pin This section describes the remote-control transmission frequency generator pin and provides its block diagram. Remote-control Transmission Frequency Generator Pin The remote-control transmission frequency generator uses the P37/BZ/RCO pin. P37/BZ/RCO pin The P37/BZ/RCO pin serves as a general-purpose I/O port pin (P37), buzzer output pin (BZ), or as remote-control transmission frequency output pin (RCO).

  • Page 311: Remote-Control Transmission Frequency Generator Registers

    CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR 13.4 Remote-control Transmission Frequency Generator Registers This section describes the registers for the remote-control transmission frequency generator. Remote-control Transmission Frequency Generator Registers Figure 13.4-1 Remote-control Transmission Frequency Generator Registers RCR1 (Remote-control transmission frequency control register 1) Address Bit 7 Bit 6...

  • Page 312: Remote-Control Transmission Frequency Control Register 1 (Rcr1)

    13.4 Remote-control Transmission Frequency Generator Registers 13.4.1 Remote-control Transmission Frequency Control Register 1 (RCR1) Remote-control transmission frequency control register 1 selects the count clock for the remote-control transmission frequency and sets the "H" width. Remote-control Transmission Frequency Control Register 1 (RCR1) Figure 13.4-2 Remote-control Transmission Frequency Control Register 1 (RCR1) Address Bit 7...
  • Page 313 CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR Table 13.4-1 Functions of Remote-control Transmission Frequency Control Register 1 (RCR1) Bits Bit name Function Set the "H" width count of the remote-control transmission frequency ("H" width compare value), which is to be compared with the counter value.

  • Page 314: Remote-Control Transmission Frequency Control Register 2 (Rcr2)

    13.4 Remote-control Transmission Frequency Generator Registers 13.4.2 Remote-control Transmission Frequency Control Register 2 (RCR2) Remote-control transmission frequency control register 2 enables remote-control transmission frequency output and sets the cycle. Remote-control Transmission Frequency Control Register 2 (RCR2) Figure 13.4-3 Remote-control Transmission Frequency Control Register 2 (RCR2) Address Bit 7 Bit 6...
  • Page 315 CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR Table 13.4-2 Functions of Remote-control Transmission Frequency Control Register 2 (RCR2) Bits Bit name Function Set the cycle count of the remote-control transmission frequency, which is to be compared with the counter value. (Value compared for cycle) Note: In case of selecting 0.5 t...

  • Page 316: Operation Of Remote-Control Transmission Frequency Generator

    13.5 Operation of Remote-control Transmission Frequency Generator 13.5 Operation of Remote-control Transmission Frequency Generator The remote-control transmission frequency generator (when serving as the 6-bit PPG) can generate a remote-control transmission frequency of the specified cycle and "H" width. Operation of Remote-control Transmission Frequency Generator Figure 13.5-1 shows the settings required to operate the remote-control transmission frequency generator as the 6-bit PPG.

  • Page 317: Figure 13.5-2 Operation Of Remote-Control Transmission Frequency Generator

    CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR Figure 13.5-2 illustrates operation of the remote-control transmission frequency generator. Figure 13.5-2 Operation of Remote-control Transmission Frequency Generator Counter value Cycle set value (RCR2: SCL0 to SCL5) “H” width set value (RCR1: HSC0 to HSC5) Cycle* “H”...

  • Page 318: Notes On Using Remote-Control Transmission Frequency Generator

    13.6 Notes on Using Remote-control Transmission Frequency Generator 13.6 Notes on Using Remote-control Transmission Frequency Generator This section gives notes on using the remote-control transmission frequency generator. Notes on Using Remote-control Transmission Frequency Generator Switching the output pin The P37/BZ/RCO pin serves as a general-purpose port, buzzer output, or remote-control transmission frequency output pin.

  • Page 319: Figure 13.6-1 Changing Set Values During Operation Of Remote-Control Transmission Frequency Generator

    CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR Figure 13.6-1 Changing Set Values during Operation of Remote-control Transmission Frequency Generator Counter value Overflow Cycle set value (RCR2: SCL) "H" width set value (RCR1: HSC) RCO output waveform 1 cycle Extended for overflow *1: Since the current counter value is smaller than the new set value, the set value remains valid in the current cycle.

  • Page 320: Figure 13.6-3 Error On Starting Counter Operation

    13.6 Notes on Using Remote-control Transmission Frequency Generator Figure 13.6-3 Error on Starting Counter Operation Counter value Count clock 1 cycle Cycle Error of 00 Counter start...

  • Page 321: Program Example For Remote-Control Transmission Frequency Generator

    CHAPTER 13 REMOTE-CONTROL TRANSMISSION FREQUENCY GENERATOR 13.7 Program Example for Remote-control Transmission Frequency Generator This section provides a program example for the remote-control transmission frequency generator. Program Example for Remote-control Transmission Frequency Generator Processing description Generates a remote-control transmission frequency of a cycle of approx. 28.6 µs and a duty •...

  • Page 322: Chapter 14 Peripheral Control Clock Output

    CHAPTER 14 PERIPHERAL CONTROL CLOCK OUTPUT This chapter describes the functions and operation of the peripheral control clock output. 14.1 Overview of Peripheral Control Clock Output 14.2 Structure of Peripheral Control Clock Output 14.3 Peripheral Control Clock Output Pin 14.4 Program Example for Peripheral Control Clock Output...

  • Page 323: 14.1 Overview Of Peripheral Control Clock Output

    CHAPTER 14 PERIPHERAL CONTROL CLOCK OUTPUT 14.1 Overview of Peripheral Control Clock Output The peripheral control clock output offers a choice of three clock signals different in frequency. Clock Output Function The clock output function outputs clock signals (square waves) for driving, for example, a peripheral LSI.

  • Page 324: 14.2 Structure Of Peripheral Control Clock Output

    14.2 Structure of Peripheral Control Clock Output 14.2 Structure of Peripheral Control Clock Output The peripheral control clock output consists of the following three blocks: • Prescalers 1 and 2 • Clock output selector • Peripheral control clock register (SCGC) Block Diagram of Peripheral Control Clock Output Figure 14.2-1 Block Diagram of Peripheral Control Clock Output Internal data bus...

  • Page 325: 14.3 Peripheral Control Clock Output Pin

    CHAPTER 14 PERIPHERAL CONTROL CLOCK OUTPUT 14.3 Peripheral Control Clock Output Pin This section describes the peripheral control clock output pin and provides its block diagram. Peripheral Control Clock Output Pin The peripheral control clock output uses the P33/EC/SCO pin. P33/EC/SCO pin The P33/EC/SCO pin serves as a general-purpose I/O port pin (P33), 8/16-bit timer/counter external clock input pin (EC), or as peripheral control clock output pin (SCO).

  • Page 326: Peripheral Control Clock Register (Scgc)

    14.3 Peripheral Control Clock Output Pin 14.3.1 Peripheral Control Clock Register (SCGC) The peripheral control clock register (SCGC) selects the peripheral control clock output frequency and also enables or disables clock output. Peripheral Control Clock Register (SCGC) Figure 14.3-2 Peripheral Control Clock Register (SCGC) Address Bit 7 Bit 6...
  • Page 327 CHAPTER 14 PERIPHERAL CONTROL CLOCK OUTPUT Table 14.3-1 Functions of Peripheral Control Clock Register (SCGC) Bits (Continued) Bit name Function • These bits select the peripheral control clock output and enable or disable clock output. • When these bits are not "00 ", the P33/EC/SCO pin serves as the peripheral control clock output pin (SCO) to output a square wave at the selected frequency.

  • Page 328: 14.4 Program Example For Peripheral Control Clock Output

    14.4 Program Example for Peripheral Control Clock Output 14.4 Program Example for Peripheral Control Clock Output This section provides a program example for the peripheral control clock output. Program Example for Peripheral Control Clock Output Processing description Outputs a square wave at a frequency of 16.384 kHz from the peripheral control clock output pin (SCO).
  • Page 329 CHAPTER 14 PERIPHERAL CONTROL CLOCK OUTPUT...

  • Page 330: Appendix

    APPENDIX The appendices include an I/O map and the instruction list. A. I/O Map B. Instructions C. Mask Options D. Programming PROM E. MB89120/120A Series Pin States...

  • Page 331: Appendix A I/O Map

    APPENDIX A I/O Map APPENDIX A I/O Map Table A lists the addresses of the registers used by the internal peripheral functions of the MB89120/120A series. I/O Map Table A-1 I/O Map Register Address Register description Read/Write Initial value name PDR0 Port 0 data register XXXXXXXX...
  • Page 332 APPENDIX A I/O Map Table A-1 I/O Map (Continued) Register Address Register description Read/Write Initial value name (Vacancy) XXXXXXXX T2CR Timer 2 control register X000XXX0 T1CR Timer 1 register X000XXX0 T2DR Timer 2 data register XXXXXXXX T1DR Timer 1 data register XXXXXXXX Serial mode register 00000000...
  • Page 333 APPENDIX A I/O Map Read/write access symbols R/W: R eadable and writable R: Read-only W: Write-only Initial value symbols 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". X: The initial value of this bit is indeterminate. M: The initial value of this bit is determined by the musk option.

  • Page 334: Appendix B Overview Of Instructions

    APPENDIX B Overview of Instructions APPENDIX B Overview of Instructions This appendix describes the F MC-8L instruction set. Overview of F MC-8L Instructions The F MC-8L has 140 signal-byte machine instructions (256 bytes on the map). Each instruction code consists of a machine instruction and operands that follow. Figure B-1 illustrates a machine code on the instruction map.
  • Page 335 APPENDIX B Overview of Instructions Table B-1 Instruction List Symbols (Continued) Symbol Meaning #d16 Immediate data (16 bits) dir: b Bit direct address (8 bits: 3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of the accumulator (8 bits) Lower 8 bits of the accumulator (8 bits)

  • Page 336: Addressing

    APPENDIX B Overview of Instructions Addressing The F MC-8L supports the following ten addressing modes: • Direct addressing • Extended addressing • Bit direct addressing • Index addressing • Pointer addressing • General-purpose register addressing • Immediate addressing • Vector addressing •...

  • Page 337: Figure B.1-3 Bit Direct Addressing

    APPENDIX B Overview of Instructions Bit direct addressing Indicated by "dir: b" in the instruction list. Used to access the area between "0000 " and "00FF " in bit units. For bit direct addressing, the upper one byte of the address is "00 ", the operand specifies the lower one byte of the address, and the lower three bits of the operation code specify the bit position.

  • Page 338: Figure B.1-6 General-Purpose Register Addressing

    APPENDIX B Overview of Instructions shows an example. Figure B.1-6 General-Purpose Register Addressing A,R6 01010 0156 Immediate addressing Indicated by "#d8" in the instruction list. Used when immediate data is required. In immediate addressing, the operand is used directly as immediate data. The operation code determines whether the data is byte or word.

  • Page 339: Figure B.1-8 Vector Addressing

    APPENDIX B Overview of Instructions Figure B.1-8 shows an example. Figure B.1-8 Vector Addressing CALLV (Conversion) FFCA FEDC FFCB Relative addressing Indicated by "rel" in the instruction list. Used to branch to a destination in the area 128 bytes above or below the program counter (PC). Relative addressing adds the sign-extended contents of the first operand to the PC and stores the result in the PC.

  • Page 340: Special Instructions

    APPENDIX B Overview of Instructions Special Instructions This section describes special instructions, other than addressing. Special Instructions JMP @A This instruction moves the address contained in the accumulator (A) to the program counter (PC) and branches to the new address. This instruction can be used to perform an N option branch by placing N branch destination addresses in a table and moving the desired address to the accumulator.

  • Page 341: Figure B.2-3 Mulu A

    APPENDIX B Overview of Instructions MULU A This instruction performs an unsigned multiplication of AL (lower 8 bits of the accumulator) and TL (lower 8 bits of the temporary accumulator) and stores the 16-bit result in A. The content of T (temporary accumulator) does not change.

  • Page 342: Figure B.2-5 Xchw A,Pc

    APPENDIX B Overview of Instructions Figure B.2-5 shows an outline of the instruction operation. Figure B.2-5 XCHW A,PC (Before execution) (After execution) 5678 1235 1234 5678 The content of A after executing this instruction is the address of the next instruction (not the address containing the operation code of this instruction).

  • Page 343: Figure B.2-7 Execution Example Of Callv #3

    APPENDIX B Overview of Instructions Figure B.2-7 shows an outline of the instruction operation. Figure B.2-7 Execution Example of CALLV #3 (Before execution) (After execution) 5678 FEDC 1234 (-2) 1232 1232 1232 1233 1233 FFC6 FFC6 FFC7 FFC7 The content of PC saved to stack area after executing this instruction is the address of next instruction (not the address containing the operation code of this instruction.) Accordingly, the value "5679 "...

  • Page 344: Bit Manipulation Instructions (Setb, Clrb)

    APPENDIX B Overview of Instructions Bit Manipulation Instructions (SETB, CLRB) The bit manipulation instructions use a different read operation to the normal operation for some bits of peripheral function registers. Read-modify-write Operation Bit manipulation instructions set to "1" (SETB) or clear to "0" (CLRB) the specified bit only of a register or RAM location.

  • Page 345: F 2 Mc-8L Instructions

    APPENDIX B Overview of Instructions MC-8L Instructions Tables B.4-1 to B.4-4 list the F MC-8L instructions. Transfer Instructions Table B.4-1 Transfer Instructions Mnemonic Operation N Z V C OP code MOV dir,A (dir) <-- (A) - - - - MOV @IX+off,A ((IX) + off ) <-- (A) - - - - MOV ext,A...

  • Page 346: Table B.4-2 Arithmetic Operation Instructions

    APPENDIX B Overview of Instructions Table B.4-1 Transfer Instructions (Continued) Mnemonic Operation N Z V C OP code MOVW A,@EP (AH) <-- ((EP)), (AL) <-- ((EP) + 1 ) + + - - MOVW A,EP (A) <-- (EP) - - - - MOVW EP,#d16 (EP) <-- d16 - - - -...
  • Page 347 APPENDIX B Overview of Instructions Table B.4-2 Arithmetic Operation Instructions (Continued) Mnemonic Operation N Z V C OP code ADDC A,@EP (A) <-- (A) + ((EP)) + C + + + + ADDCW A (A) <-- (A) + (T) + C + + + + ADDC A (AL) <-- (AL) + (TL) + C...

  • Page 348: Table B.4-3 Branch Instructions

    APPENDIX B Overview of Instructions Table B.4-2 Arithmetic Operation Instructions (Continued) Mnemonic Operation N Z V C OP code (A) <-- (AL) ∀ d8 XOR A,#d8 + + R - (A) <-- (AL) ∀ (dir) XOR A,dir + + R - (A) <-- (AL) ∀...

  • Page 349: Table B.4-4 Other Instructions

    APPENDIX B Overview of Instructions Table B.4-3 Branch Instructions (Continued) Mnemonic Operation N Z V C OP code BBC dir: b,rel If (dir: b) = 0 then PC <-- PC + rel - + - - B0 to B7 BBS dir: b,rel If (dir: b) = 1 then PC <-- PC + rel - + - - B8 to BF...
  • Page 350 APPENDIX B Overview of Instructions Table B.4-5 Instruction List Columns (Continued) Column Description Operation Operation of an instruction A content change (automatic transfer from A to T) when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: •...

  • Page 351: Instruction Map

    APPENDIX B Overview of Instructions Instruction Map Table B.5-1 lists the F MC-8L instruction map. Instruction Map Table B.5-1 F MC-8L Instruction Map SWAP RETI PUSHW POPW MOVW CLRI SETI CLRB INCW DECW MOVW dir: A,ext A,PS dir: 0 A,PC 0,rel MULU DIVU...
  • Page 352 APPENDIX B Overview of Instructions Table B.5-1 F MC-8L Instruction Map (Continued) ADDC SUBC SETB CALLV dir: A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 5,rel ADDC SUBC SETB CALLV dir: A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6...

  • Page 353: Appendix C Mask Options

    APPENDIX C Mask Options APPENDIX C Mask Options This appendix lists the mask options for the MB89120/120A series. Mask Options List Table C-1 Mask Options List MB89123A MB89P131 Part number MB89121 MB89P135A MB89PV130A MB89125A MB89P133A Set with EPROM Setting not Specifying procedure Specify when ordering masking programmer...

  • Page 354: Table C-2 Standard Options

    APPENDIX C Mask Options Common type also available for crystal/ceramic oscillation For peripheral control clock output with P33 (39 pin) as SCO, select "Use". The products other than the MB89121 can be used only by software setting. Table C-2 Standard Options Model option MB89P131-101 MB89P133A-201...

  • Page 355: Appendix D Programming Prom

    APPENDIX D Programming PROM APPENDIX D Programming PROM In PROM mode, the MB89P131, MB89P133A, and MB89P135A function equivalent to the MBM27C256A. This allows the ROM to be programmed with a general-purpose ROM programmer by using the dedicated adaptor. Note that the electronic signature mode cannot be used.

  • Page 356: Programming One-Time Prom

    APPENDIX D Programming PROM Programming One-time PROM This section explains how to program the PROM to be mounted on the MB89P133A, MB89P131, or MB89P135A. ROM Programmer Socket Adaptor and Recommended ROM Programmers Connect the jumper pin on the adaptor to V Depending on the ROM programmer, inserting a capacitor of about 0.1 µF between V or V and V...

  • Page 357: Figure D.1-1 Memory Map In Prom Mode (Mb89P131)

    APPENDIX D Programming PROM Memory Map in PROM Mode Figures D.1-1 to D.1-3 show the memory map in PROM mode. Figure D.1-1 Memory Map in PROM Mode (MB89P131) Normal operation PROM mode (MB89P131) (Corresponding addresses on the ROM programmer) 0000 Not available 0000 Not available...

  • Page 358: Figure D.1-3 Memory Map In Prom Mode (Mb89P135A)

    APPENDIX D Programming PROM Figure D.1-3 Memory Map in PROM Mode (MB89P135A) Normal operation PROM mode (MB89P135A) (Corresponding addresses on the PROM programmer) 0000 Not available 8000 0000 Not available Not available 8FF0 3FF0 Not available Option area 8FF6 3FF6 Not available Not available 4000...

  • Page 359: Table D.1-2 Prom Option Bit Map

    APPENDIX D Programming PROM PROM Options Bit Map MB89P135A Table D.1-2 PROM Option Bit Map Vacancy Vacancy Vacancy Clock Oscillation stabilization Reset pin Power-on mode delay time output reset 3FF0 Readable Readable Readable selection 1: Yes 1: Yes 00: 2 10: 2 1: Single 0: No...

  • Page 360: Figure D.1-4 Screening Flowchart

    + 150 ˚ C, 48 Hrs. Read data Assembly Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked one-time PROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.

  • Page 361: Programming Eprom With Piggyback/Evaluation Device

    APPENDIX D Programming PROM Programming EPROM with Piggyback/Evaluation Device This section describes the programming to the EPROM with piggyback/evaluation device. EPROM for Use MBM27C256A-20TVM Programming Socket Adapter To program to the PROM using a ROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below.
  • Page 362 APPENDIX D Programming PROM Programming to the EPROM 1. Set the EPROM programmer to the MBM27C256A. 2. Load program data into the EPROM programmer at 0000 to 7FFF 3. Program with the EPROM programmer.

  • Page 363: Appendix Emb89120 Series Pin States

    APPENDIX E MB89120 Series Pin States APPENDIX E MB89120 Series Pin States This section describes the pin states of the MB89120/120A series in each mode. Pin States in Each Mode Table E-1 Pin States in Each Mode Normal Stop mode Stop mode Watc Sleep mode...
  • Page 364 APPENDIX E MB89120 Series Pin States SPL: Pin state specification bit in the standby control register (STBC) Hold: The pin set as output holds its state (level) immediately before changing to each mode.
  • Page 365 APPENDIX E MB89120 Series Pin States...

  • Page 366: Index

    INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
  • Page 367 INDEX Index Numerics clock gear function (main clock speed select function) ............69 16-bit data on stack, storing ........31 clock generator ............61 16-bit operand, storing ........... 30 clock mode, operating states in ......68 6-bit PPG function (iIn case of selecting 1/8/32 clock output gunction ...........
  • Page 368 INDEX external interrupt circuit 2 interrupt, register and interval timer function (timebase timer), vector table for ........... 255 operation of ..........139 external interrupt circuit 2 pin....... 249 interval timer function (watch interrupt) ....262 external interrupt circuit 2 pin, block diagram of .. 250 interval timer function, interrupt for .......138 external interrupt circuit 2 register......
  • Page 369 INDEX peripheral control clock output, block diagram of. 297 read-modify-write operation ......... 317 peripheral control clock output, recommended ROM programmer ......329 program example for ........301 recommended screening condition ...... 332 peripheral control clock register (SCGC)....299 register and vector table for timebase piggyback/evaluation product.......
  • Page 370 INDEX stack operation at start of interrupt processing ..51 timer 1 control register (T1CR) ......166 standby control register (STBC)......81 timer 1 data register (T1DR).........171 standby mode ............73 timer 2 data register (T2DR).........173 standby mode and interrupt, changing to....93 timer control 2 register (T2CR) ......169 standby mode by interrupt, wake-up from....
  • Page 371 INDEX...
  • Page 372 CM25-10111-3E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL MC-8L 8-BIT MICROCONTROLLER MB89120/120A SERIES HARDWARE MANUAL February 2000 the third edition FUJITSU LIMITED Electronic Devices Published Edited Technical Communication Dept.

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