Fujitsu F2MC-16LX Hardware Manual page 397

At reset, the settings will be initialized to "000". These bits cannot be rewritten while data
transfer is in progress.
The shift clock can be selected from among five internal clocks and one external clock.
Shifting is performed externally. The combinations of SMD2, 1, 0 = "110" and "111" are
reserved and must not be set.
Shifting can also be performed for individual instructions by setting SC0E = 0 to select the
clock and using a port that shares the pins SCK1 and SCK2.
[Bit 12] SIE: Serial I/O Interrupt Enable
This bit controls serial I/O interrupt requests as shown below.
0 Serial I/O interrupts prohibited (initial value)
1 Serial I/O interrupts allowed
• This bit is initialized to "0" at reset
• This bit can be read and written.
[Bit 11] SIR: Serial I/O Interrupt Request
This bit is set to "1" when serial data transfer ends. When this bit becomes "1" in the interrupt
enabled state (SIE = "1"), an interrupt request to the CPU will be generated. The condition
for clearing this bit depends on the MODE bit:
• Cleared by setting the SIR bit to "0" in a write operation when the MODE bit is "0".
• Cleared by reading the SDR or by writing, when the MODE bit is "1".
• Cleared by reset or by writing "1" for the STOP bit regardless of the value of the MODE bit.
• Writing "1" for this bit has no effect.
• Read-modify-write instructions always return "1".
[Bit 10] BUSY (transfer status display)
This bit indicates whether serial transfer is currently being executed.
BUSY
Operation is stopped or the serial data register is in the R/W wait state
0
(initial value)
1 Serial transfer take place
• This bit is initialized to "0" at reset.
• This bit can only be read.
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE
Operation state
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