Fujitsu F2MC-16LX Hardware Manual page 291

I Block diagram of PWC timer
Figure 14.1-1 "Block diagram of the PWC timer" shows a block diagram of the PWC timer.
PWCR read
Reload
Data transfer
Overflow
Control circuit
Measurement
start edge
Measurement
end edge
Measurement end
interrupt request
Overflow interrupt request
15
Figure 14.1-1 Block diagram of the PWC timer
Error
ERR
detection
PWCR
16
16
16-bit up-count timer
Start edge End edge
selection selection
Divide ON/OFF
Edge
detection
PIS0/PIS1
ERR CKS0/CKS1
PWCSR
2
Clock
Timer
CKS1/CKS0
clear
Count enabled
8-bit
divider
Divide ratio selection
DIVR
CHAPTER 14 PWC TIMER
Internal clock(machine clock/4)
2
2
Clock divider
3
2
Divider clear
Input
PWC0
waveform
PWC1
comparator
275