Fujitsu F2MC-16LX Hardware Manual page 565
Mb90470 series 16-bit microcontroller
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Also See for F2MC-16LX:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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Table B.8-16 21 Bit operand instructions
Mnemonic
#
MOVB
A,dir:bp
3
MOVB
A,addr16:bp
4
MOVB
A,io:bp
3
MOVB
dir:bp,A
3
MOVB
addr16:bp,A
4
MOVB
io:bp,A
3
SETB
dir:bp
3
SETB
addr16:bp
4
SETB
io:bp
3
CLRB
dir:bp
3
CLRB
addr16:bp
4
CLRB
io:bp
3
BBC
dir:bp,rel
4
BBC
addr16:bp,rel
5
BBC
io:bp,rel
4
BBS
dir:bp,rel
4
BBS
addr16:bp,rel
5
BBS
io:bp,rel
4
SBBS
addr16:bp,rel
5
WBTS
io:bp
3
WBTC
io:bp
3
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
Table B.8-17 6 Accumulator operation instructions (byte, word)
Mnemonic
#
SWAP
1
SWAPW / XCHW A,T
1
EXT
1
EXTW
1
ZEXT
1
ZEXTW
1
RG
B
5
0
(b)
byte (A) <-- (dir:bp)b
5
0
(b)
byte (A) <-- (addr16:bp)b
4
0
(b)
byte (A) <-- (io:bp)b
7
0
2 x (b)
bit (dir:bp)b <-- (A)
7
0
2 x (b)
bit (addr16:bp)b <-- (A)
6
0
2 x (b)
bit (io:bp)b <-- (A)
7
0
2 x (b)
bit (dir:bp)b <-- 1
7
0
2 x (b)
bit (addr16:bp)b <-- 1
7
0
2 x (b)
bit (io:bp)b <-- 1
7
0
2 x (b)
bit (dir:bp)b <-- 0
7
0
2 x (b)
bit (addr16:bp)b <-- 0
7
0
2 x (b)
bit (io:bp)b <-- 0
*1
0
(b)
Branch on (dir:bp) b = 0
*1
0
(b)
Branch on (addr16:bp) b = 0
*2
0
(b)
Branch on (io:bp) b = 0
*1
0
(b)
Branch on (dir:bp) b = 1
*1
0
(b)
Branch on (addr16:bp) b = 1
*1
0
(b)
Branch on (io:bp) b = 1
*3
0
2 x (b)
Branch on (addr16:bp) b = 1, bit = 1
*4
0
*5
Waits until (io:bp) b = 1
*4
0
*5
Waits until (io:bp) b = 0
RG
B
3
0
0
byte (A)0-7 <--> (A)8-15
2
0
0
word (AH) <--> (AL)
1
0
0
Byte sign extension
2
0
0
Word sign extension
1
0
0
Byte zero extension
1
0
0
Word zero extension
Operation
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Operation
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APPENDIX B Instructions
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