Fujitsu F2MC-16LX Hardware Manual page 447

[Bit 8] INT: INTerrupt
This bit is used as a transfer end interrupt request flag.
(During writing)
0
1
(During reading)
0
1
If this bit is "1", the SCL line is kept at the "L" level. This bit is cleared by writing "0" before
the SCL line is opened for transfer of the next byte. Alternatively, this bit is reset to "0" if, in
master mode, a start or stop condition is generated.
I Notes on using the bus control register (IBCR)
The following precautions relate to conflicts among the SCC, MSS, and INT bits.
Writing to the SCC, MSS, and INT bits at the same time will cause a conflict between transfer of
the next byte and generation of start or stop conditions. In this case, the priority is specified as
follows.
❍ Next byte transfer and stop condition generation
If the INT and MSS bits are set to "0", setting of the MSS bit to "0" has priority and the stop
condition is generated.
❍ Next byte transfer and start condition generation
If the INT bit is set to "0" and the SCC bit is set to "1", setting of the SCC bit to "1" has priority
and the start condition is generated.
❍ Start condition generation and stop condition generation
Setting the SCC bit to "1" and the MSS bit to "0" at the same time is prohibited.
Clears the transfer end interrupt request flag
Not applicable
Transfer has not ended
This bit is set if the following conditions are met when one byte including an
acknowledge bit is transferred:
• Byte transferred in bus master transfer
• Byte transferred in slave mode with addressing
• General call address is received
• Arbitration lost occurs
• Attempt to generate a start condition while other systems use the bus.
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CHAPTER 22 I C INTERFACE
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