Fujitsu F2MC-16LX Hardware Manual page 131

Mb90470 series 16-bit microcontroller

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multiplied by one can be specified.

PLL oscillation can be between 3 and 20 MHz. This oscillation range varies depending on

operating voltage and the multiplication rate.

I Clock supply map

Machine clocks generated by the clock generator are supplied as operation clocks of the CPU

and peripheral functions. Therefore, operations of the CPU and peripheral functions are affected

by changes between the main clock and PLL clock (clock mode) and by changes in the PLL

clock multiplication rate. The clock-divided outputs of the timebase timer are supplied to some

peripheral functions, and the peripheral functions can select their own operation clocks. Figure

5.1-1 "Clock supply map" shows a clock supply map.

HCLK : Oscillation clock

MCLK : Main clock

SCLK : Sub clock

PCLK : PLL clock

: Machine clock

Figure 5.1-1 Clock supply map

Timebase timer

PLL multiplier circuit

Clock divided

Clock divided

Clock selector

Peripheral functions

Watchdog timer

8/16-bit PPG

8/16-bit PPG

8/16-bit PPG

16-bit reload

I/O extensive

serial interface

Chip selection

16-bit output

16-bit free-

running timer

16-bit input

External interrupt

stabilization wait

CHAPTER 5 CLOCKS